Sadahiro Tani

11 papers A* 1Journal 6Unranked 4
YearRankTypeTitle / Venue / Authors
2024 J jnl
A Multi-Channel Biomedical Sensor System with System-Level Chopping and Stochastic A/D Conversion.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yusaku Hirai, Toshimasa Matsuoka, Takatsugu Kamata, Sadahiro Tani, Takao Onoye
2019 J jnl
A Biomedical Sensor System With Stochastic A/D Conversion and Error Correction by Machine Learning.
IEEE Access
Yusaku Hirai, Toshimasa Matsuoka, Sadahiro Tani, Shodai Isami, Keiji Tatsumi, Masayuki Ueda, Takatsugu Kamata
2017 — conf
A calibration with an adaptive data selection based on Bayes estimation for a successive stochastic approximation ADC system.
IFSA-SCIS
Keiji Tatsumi, Toshimasa Matsuoka, Sadahiro Tani
2017 — conf
An analog front-end employing 87 dB SNDR stochastic SAR-ADC for a biomedical sensor.
NEWCAS
Takatsugu Kamata, Masayuki Ueda, Yusaku Hirai, Sadahiro Tani, Tomohiro Asano, Shodai Isami, Toshifumi Kurata, Keiji Tatsumi, Toshimasa Matsuoka
2017 J jnl
Behavior-Level Analysis of a Successive Stochastic Approximation Analog-to-Digital Conversion System for Multi-Channel Biomedical Data Acquisition.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Sadahiro Tani, Toshimasa Matsuoka, Yusaku Hirai, Toshifumi Kurata, Keiji Tatsumi, Tomohiro Asano, Masayuki Ueda, Takatsugu Kamata
2016 J jnl
An offset distribution modification technique of stochastic flash ADC.
IEICE Electron. Express
Tomohiro Asano, Yusaku Hirai, Sadahiro Tani, Shinya Yano, Ikkyun Jo, Toshimasa Matsuoka
2005 — conf
Interconnect capacitance extraction for system LCD circuits.
ACM Great Lakes Symposium on VLSI
Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa
2003 J jnl
Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai
2002 — conf
Parasitic capacitance modeling for multilevel interconnects.
APCCAS (1)
Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai
1981 J jnl
A Layout System for the Random Logic Portion of an MOS LSI Chip.
IEEE Trans. Computers
Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki
1980 A* conf
A layout system for the random logic portion of MOS LSI.
DAC
Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki