Sachin Taneja - RankMe

27 papers A* 1C 1Journal 10Unranked 15

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	HERACLES: 8192-Way SIMD Programmable Scalable Fully-Homomorphic Encryption SoC for Privacy-Preserving Cloud Computing in Intel 3 CMOS. ISSCC Anupam Golder, Raghavan Kumar, Sachin Taneja, Kylan Race, Paolo A. Aseron, James Greensky, Wen Wang, Huijing Gong, Lalith Kethareswaran, Vikram B. Suresh, Adish Vartak, AppaRao Challagundla, Jeremy Casas, Poornima Lalwaney, Duhyeong Kim, Christopher N. Gutierrez, Ernesto Zamora Ramos, Wonhee Cho, Jose M. Rojas Chaves, Michael Steiner, Dan Lake, Nataraj Yennampelli, Karthik Nivarthi, Kamalakanth Bijinapally, Bala Prasad Talamala, Sravanth Valluri, Vasantha Srirambhatla, Chris Wilkerson, Rosario Cammarota, Sanu Mathew
2026	J	`jnl`	Side-Channel Attack-Resistant HMAC-SHA256 Accelerator With Boolean and Arithmetic Masking in Intel 4 CMOS. IEEE J. Solid State Circuits Sachin Taneja, Vikram B. Suresh, Raghavan Kumar, Vivek De, Sanu K. Mathew
2025	—	`conf`	A 2455μm CICC Sachin Taneja, Vikram B. Suresh, Raghavan Kumar, Vivek De, Sanu Mathew
2025	J	`jnl`	A 4.7-to-5.3-Gb/s Fault-Injection and Side-Channel Attack-Resistant AES-256 Engine Using Masked Isomorphic Composite Fields in Intel 4 CMOS. IEEE J. Solid State Circuits Raghavan Kumar, Sachin Taneja, Vivek De, Sanu K. Mathew
2024	J	`jnl`	A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS. IEEE J. Solid State Circuits Raghavan Kumar, Avinash L. Varna, Carlos Tokunaga, Sachin Taneja, Vivek De, Sanu K. Mathew
2024	—	`conf`	A 4.7-to-5.3Gbps Fault-Injection Attack Resistant AES-256 Engine Using Isomorphic Composite Fields in Intel 4 CMOS. VLSI Technology and Circuits Raghavan Kumar, Sachin Taneja, Vivek De, Sanu Mathew
2024	A*	`conf`	UFC: A Unified Accelerator for Fully Homomorphic Encryption. MICRO Minxuan Zhou, Yujin Nam, Xuan Wang, Youhak Lee, Chris Wilkerson, Raghavan Kumar, Sachin Taneja, Sanu Mathew, Rosario Cammarota, Tajana Rosing
2023	—	`conf`	218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS. VLSI Technology and Circuits Sachin Taneja, Vikram B. Suresh, Raghavan Kumar, Vivek De, Sanu Mathew
2023	—	`conf`	A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS. ISSCC Raghavan Kumar, Avinash Varna, Carlos Tokunaga, Sachin Taneja, Vivek De, Sanu Mathew
2023	J	`jnl`	A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. IEEE J. Solid State Circuits Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu K. Mathew
2023	—	`conf`	ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm. VLSI Technology and Circuits Joydeep Basu, Sachin Taneja, Viveka Konandur Rajanna, Tianqi Wang, Massimo Alioto
2023	—	`conf`	Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm. VLSI Technology and Circuits Animesh Gupta, Sayan Kumar, Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto
2022	—	`conf`	A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. VLSI Technology and Circuits Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu Mathew
2022	J	`jnl`	In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security. IEEE J. Solid State Circuits Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto
2021	—	`conf`	36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security. ISSCC Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto
2021	J	`jnl`	Fully Synthesizable Unified True Random Number Generator and Cryptographic Core. IEEE J. Solid State Circuits Sachin Taneja, Massimo Alioto
2021	J	`jnl`	PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion. IEEE J. Solid State Circuits Sachin Taneja, Massimo Alioto
2021	—	`conf`	SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm ESSCIRC Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto
2021	—	`conf`	SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm ESSDERC Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto
2020	C	`conf`	Deep Sub-pJ/Bit Low-Area Energy-Security Scalable SIMON Crypto-Core in 40 nm. ISCAS Sachin Taneja, Massimo Alioto
2019	—	`conf`	Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems : (Invited Paper). CICC Massimo Alioto, Sachin Taneja
2019	—	`conf`	PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion. ESSCIRC Sachin Taneja, Massimo Alioto
2019	J	`jnl`	Token-Based Security for the Internet of Things With Dynamic Energy-Quality Tradeoff. IEEE Internet Things J. Muhammad Naveed Aman, Sachin Taneja, Biplab Sikdar, Kee Chaing Chua, Massimo Alioto
2018	J	`jnl`	Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm. IEEE J. Solid State Circuits Sachin Taneja, Anastacia B. Alvarez, Massimo Alioto
2018	J	`jnl`	Ultra-Low Power Crypto-Engine Based on Simon 32/64 for Energy- and Area-Constrained Integrated Systems. CoRR Sachin Taneja, Massimo Alioto
2017	—	`conf`	A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm. A-SSCC Sachin Taneja, Anastacia B. Alvarez, Gopalakrishnan Sadagopan, Massimo Alioto
2015	—	`conf`	A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology. SoCC Vaibhav Verma, Sachin Taneja, Pritender Singh, Sanjeev Kumar Jain