Sachin S. Sapatnekar

472 papers A* 49A 87B 4C 16Misc 9Journal 182Unranked 112

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Accelerating Electrostatics-based Global Placement with Enhanced FFT Computation. ASP-DAC Hangyu Zhang, Sachin S. Sapatnekar
2026	J	`jnl`	COmPOSER: Circuit Optimization of mm-wave/RF circuits with Performance-Oriented Synthesis for Efficient Realizations. CoRR Subhadip Ghosh, Surya Srikar Peri, S. Ramprasath, Sosina A. Berhan, Endalk Y. Gebru, Ramesh Harjani, Sachin S. Sapatnekar
2026	—	`conf`	Chiplet-NAS: Chiplet-aware Neural Architecture Search for Efficient AI Inference on 2.5D Integration. ASP-DAC Cheng Guo, Pragnya Sudershan Nalla, Nikhil K. Cherukuri, Rui Xue, Sachin S. Sapatnekar, Chaitali Chakrabarti, Yu Cao, Jeff Zhang
2026	J	`jnl`	Decomposing Large-Scale Ising Problems on FPGAs: A Hybrid Hardware Approach. CoRR Ruihong Yin, Yue Zheng, Chaohui Li, Ahmet Efe, Abhimanyu Kumar, Ziqing Zeng, Ulya R. Karpuzcu, Sachin S. Sapatnekar, Chris H. Kim
2026	J	`jnl`	Extractive summarization on a CMOS Ising machine. CoRR Ziqing Zeng, Abhimanyu Kumar, Ahmet Efe, Ruihong Yin, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar
2026	—	`conf`	Invited: Toward Accurate, Large-scale Electromigration Analysis and Optimization in Integrated Systems. ISPD Sachin S. Sapatnekar
2026	J	`jnl`	Invited: Toward Accurate, Large-scale Electromigration Analysis and Optimization in Integrated Systems. CoRR Sachin S. Sapatnekar
2025	J	`jnl`	Accelerating Electrostatics-based Global Placement with Enhanced FFT Computation. CoRR Hangyu Zhang, Sachin S. Sapatnekar
2025	A	`conf`	Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables. DATE Subhadip Ghosh, Endalk Y. Gebru, Chandramouli V. Kashyap, Ramesh Harjani, Sachin S. Sapatnekar
2025	J	`jnl`	Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables. CoRR Subhadip Ghosh, Endalk Y. Gebru, Chandramouli V. Kashyap, Ramesh Harjani, Sachin S. Sapatnekar
2025	J	`jnl`	An Analytical Solution for Transient Electromigration Stress in Multisegment Straight-line Interconnects Based on a Stress-wave Model. ACM Trans. Design Autom. Electr. Syst. Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestoras E. Evmorfopoulos, Sachin S. Sapatnekar
2025	A	`conf`	CLAIRE: Composable Chiplet Libraries for AI Inference. DATE Pragnya Sudershan Nalla, Emad Haque, Yaotian Liu, Sachin S. Sapatnekar, Jeff Zhang, Chaitali Chakrabarti, Yu Cao
2025	J	`jnl`	DROID: Discrete-Time Simulation for Ring-Oscillator-Based Ising Design. CoRR Abhimanyu Kumar, S. Ramprasath, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar
2025	A*	`conf`	Invited: EDA for Heterogeneous Integration. DAC Emad Haque, Pragnya Sudershan Nalla, Chetal Choppali Sudarshan, Divya Yogi, Hangyu Zhang, Chaitali Chakrabarti, Vidya A. Chhabria, Ramesh Harjani, Jeff Zhang, Sachin S. Sapatnekar
2025	—	`conf`	Invited: Toward an ML EDA Commons: Establishing Standards, Accessibility, and Reproducibility in ML-driven EDA Research. ISPD Vidya A. Chhabria, Jiang Hu, Andrew B. Kahng, Sachin S. Sapatnekar
2025	A	`conf`	ML-Based AIG Timing Prediction to Enhance Logic Optimization. DATE Wenjing Jiang, Jin Yan, Sachin S. Sapatnekar
2025	J	`jnl`	Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar
2025	J	`jnl`	Mobile-PBR: A 28-nm Energy-Efficient Rendering Processor for Photorealistic Augmented Reality With Inverse Rendering and Background Clustering. IEEE J. Solid State Circuits Shiyu Guo, Yuhao Ju, Xi Chen, Sachin S. Sapatnekar, Jie Gu
2025	J	`jnl`	On Solving Structured SAT on Ising Machines: A Semiprime Factorization Study. CoRR Ahmet Efe, Hüsrev Cilasun, Abhimanyu Kumar, Nafisa Sadaf Prova, Ziqing Zeng, Tahmida Islam, Ruihong Yin, Chaohui Li, Peter Kreye, Chris H. Kim, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2025	A	`conf`	Optimal Selection and Placement of Voltage Regulators in 2.5D Heterogeneously Integrated Systems. ICCAD Hangyu Zhang, Divya Yogi, Ramesh Harjani, Sachin S. Sapatnekar
2025	J	`jnl`	Performance Analysis of CNN Inference/Training with Convolution and Non-Convolution Operations on ASIC Accelerators. ACM Trans. Design Autom. Electr. Syst. Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Sean Kinzer, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang
2025	J	`jnl`	The Case for Secure Miniservers Beyond the Edge. IEEE Trans. Computers Salonik Resch, Hüsrev Cilasun, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv, Jianping Wang, Sachin S. Sapatnekar, Ismail Akturk, Ulya R. Karpuzcu
2025	J	`jnl`	Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity. CoRR Emad Haque, Pragnya Sudershan Nalla, Jeff Zhang, Sachin S. Sapatnekar, Chaitali Chakrabarti, Yu Cao
2025	—	`conf`	Towards Designing and Deploying Ising Machines. ISPD Sachin S. Sapatnekar
2024	—	`conf`	2.5 A 28nm Physical-Based Ray-Tracing Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering for Mobile Devices. ISSCC Shiyu Guo, Sachin S. Sapatnekar, Jie Gu
2024	J	`jnl`	A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. ACM Trans. Design Autom. Electr. Syst. Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar
2024	J	`jnl`	An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators. ACM Trans. Design Autom. Electr. Syst. Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng
2024	A	`conf`	Analyzing the Impact of FinFET Self-Heating on the Performance of RF Power Amplifiers. ICCAD Nibedita Karmokar, Sai-Wang Tam, Thanh Viet Dinh, Vidya A. Chhabria, Ramesh Harjani, Sachin S. Sapatnekar
2024	B	`conf`	Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. ASPDAC Kishor Kunal, Jitesh Poojary, S. Ramprasath, Ramesh Harjani, Sachin S. Sapatnekar
2024	J	`jnl`	Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar
2024	A*	`conf`	ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI. HPCA Chetan Choppali Sudarshan, Nikhil Matkar, Sarma B. K. Vrudhula, Sachin S. Sapatnekar, Vidya A. Chhabria
2024	A	`conf`	Generative Methods in EDA: Innovations in Dataset Generation and EDA Tool Assistants. ICCAD Vidya A. Chhabria, Bing-Yue Wu, Utsav Sharma, Kishor Kunal, Austin Rovinski, Sachin S. Sapatnekar
2024	A	`conf`	Hardware Acceleration of Inference on Dynamic GNNs. ISLPED Sudipta Mondal, Sachin S. Sapatnekar
2024	—	`conf`	IR-Aware ECO Timing Optimization Using Reinforcement Learning. MLCAD Wenjing Jiang, Vidya A. Chhabria, Sachin S. Sapatnekar
2024	J	`jnl`	IR-Aware ECO Timing Optimization Using Reinforcement Learning. CoRR Vidya A. Chhabria, Wenjing Jiang, Sachin S. Sapatnekar
2024	J	`jnl`	ML-based AIG Timing Prediction to Enhance Logic Optimization. CoRR Wenjing Jiang, Jin Yan, Sachin S. Sapatnekar
2024	J	`jnl`	MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2024	A*	`conf`	On Error Correction for Nonvolatile Processing-In-Memory. ISCA Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv, Brandon Zink, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2024	A	`conf`	On Gate Flip Errors in Computing-In-Memory. DATE Zamshed I. Chowdhury, Hüsrev Cilasun, Salonik Resch, Masoud Zabihi, Yang Lv, Brandon Zink, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2024	J	`jnl`	On Heterogeneous Ising Machines. CoRR Hüsrev Cilasun, Abhimanyu Kumar, Ziqing Zeng, Nafisa Sadaf Prova, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2024	Misc	`conf`	OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education. VTS Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Rongjian Liang, Haoxing Ren, Sachin S. Sapatnekar, Bing-Yue Wu
2024	B	`conf`	Reinforcing the Connection between Analog Design and EDA (Invited Paper). ASPDAC Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar
2024	—	`conf`	Software-Hardware Codesign of Ray-Tracing Accelerator for Edge AR/VR With Viewpoint-Focused 3D Construction and Efficient Data Structure. MWSCAS Shiyu Guo, Sachin S. Sapatnekar, Jie Gu
2024	—	`conf`	Stress-based Electromigration Modeling in IC Design: Moving from Theory to Practice. SMACD Susann Rothe, Jens Lienig, Sachin S. Sapatnekar
2023	J	`jnl`	3SAT on an All-to-All-Connected CMOS Ising Solver Chip. CoRR M. Hüsrev Cilasun, Ziqing Zeng, Ramprasath S, Abhimanyu Kumar, Hao Lo, William Cho, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar
2023	J	`jnl`	A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. ACM Trans. Design Autom. Electr. Syst. Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar
2023	J	`jnl`	A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. CoRR Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar
2023	A	`conf`	A Multicore GNN Training Accelerator. ISLPED Sudipta Mondal, Ramprasath S, Ziqing Zeng, Kishor Kunal, Sachin S. Sapatnekar
2023	J	`jnl`	A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Ziqing Zeng, Sachin S. Sapatnekar
2023	J	`jnl`	An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators. CoRR Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng
2023	—	`conf`	Analysis of Pattern-dependent Rapid Thermal Annealing Effects on SRAM Design. ISQED Vidya A. Chhabria, Sachin S. Sapatnekar
2023	A	`conf`	AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells. DATE Sumanth Kamineni, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar, Benton H. Calhoun
2023	J	`jnl`	Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
2023	J	`jnl`	Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks. ACM Trans. Design Autom. Electr. Syst. Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
2023	A	`conf`	Energy-efficient Hardware Acceleration of Shallow Machine Learning Applications. DATE Ziqing Zeng, Sachin S. Sapatnekar
2023	J	`jnl`	Experimental demonstration of magnetic tunnel junction-based computational random-access memory. CoRR Yang Lv, Brandon R. Zink, Robert P. Bloom, M. Hüsrev Cilasun, Pravin Khanal, Salonik Resch, Zamshed I. Chowdhury, Ali Habiboglu, Weigang Wang, Sachin S. Sapatnekar, Ulya R. Karpuczu, Jianping Wang
2023	A	`conf`	Frequency-Domain Transient Electromigration Analysis Using Circuit Theory. ICCAD Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestoras E. Evmorfopoulos, Sachin S. Sapatnekar
2023	J	`jnl`	GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2023	—	`conf`	MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. MLCAD Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2023	A	`conf`	Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor Arrays. DATE Nibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar
2023	A*	`conf`	On Endurance of Processing in (Nonvolatile) Memory. ISCA Salonik Resch, M. Hüsrev Cilasun, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2023	J	`jnl`	Performance Analysis of DNN Inference/Training with Convolution and non-Convolution Operations. CoRR Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Sean Kinzer, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang
2023	J	`jnl`	Performance-driven Wire Sizing for Analog Integrated Circuits. ACM Trans. Design Autom. Electr. Syst. Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2023	—	`conf`	PimCity: A Compute in Memory Substrate featuring both Row and Column Parallel Computing. ICRC Salonik Resch, Hüsrev Cilasun, Masoud Zabihi, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2023	—	`conf`	Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment Interconnects. ISPD Nestor E. Evmorfopoulos, Mohammad Abdullah Al Shohel, Olympia Axelou, Pavlos Stoikos, Vidya A. Chhabria, Sachin S. Sapatnekar
2023	—	`conf`	Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators. ASP-DAC Susmita Dey Manasi, Suvadeep Banerjee, Abhijit Davare, Anton A. Sorokin, Steven M. Burns, Desmond A. Kirkpatrick, Sachin S. Sapatnekar
2023	—	`conf`	The ALIGN Automated Analog Layout Engine: Progress, Learnings, and Open Issues. ISPD Sachin S. Sapatnekar
2023	J	`jnl`	Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems. CoRR Vidya A. Chhabria, Chetan Choppali Sudarshan, Sarma B. K. Vrudhula, Sachin S. Sapatnekar
2023	—	`conf`	Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. ESSDERC Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani
2022	A	`conf`	A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. DATE Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar
2022	A	`conf`	A Novel Semi-Analytical Approach for Fast Electromigration Stress Analysis in Multi-Segment Interconnects. ICCAD Olympia Axelou, Nestor E. Evmorfopoulos, George Floros, George I. Stamoulis, Sachin S. Sapatnekar
2022	—	`conf`	Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. ISPD Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar
2022	A	`conf`	Are Analytical Techniques Worthwhile for Analog IC Placement? DATE Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2022	J	`jnl`	CRAM-Seq: Accelerating RNA-Seq Abundance Quantification Using Computational RAM. IEEE Trans. Emerg. Top. Comput. Zamshed I. Chowdhury, S. Karen Khatamifard, Salonik Resch, M. Hüsrev Cilasun, Zhengyang Zhao, Masoud Zabihi, Meisam Razaviyayn, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2022	—	`conf`	Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. ASP-DAC Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar
2022	A	`conf`	Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. DATE Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
2022	—	`conf`	EDAML 2022 Invited Speaker 7: Analog and Digital Circuit and Layout Optimization using Machine Learning. IPDPS Workshops Sachin S. Sapatnekar
2022	J	`jnl`	Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions. ACM Trans. Embed. Comput. Syst. Salonik Resch, S. Karen Khatamifard, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, M. Hüsrev Cilasun, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2022	J	`jnl`	Error Detection and Correction for Processing in Memory (PiM). CoRR M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv, Brandon Zink, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2022	—	`conf`	From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction. MLCAD Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar
2022	A*	`conf`	GNNIE: GNN inference engine with load-balancing and graph-specific caching. DAC Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Sachin S. Sapatnekar
2022	J	`jnl`	OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vidya A. Chhabria, Sachin S. Sapatnekar
2022	—	`conf`	Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms. MLCAD Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng
2021	—	`conf`	A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing. MLCAD Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2021	J	`jnl`	A Linear-Time Algorithm for Steady-State Analysis of Electromigration in General Interconnects. CoRR Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar
2021	A*	`conf`	A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects. DAC Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar
2021	J	`jnl`	A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects. CoRR Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar
2021	J	`jnl`	A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control. IEEE J. Solid State Circuits Luke R. Everson, Sachin S. Sapatnekar, Chris H. Kim
2021	J	`jnl`	ALIGN: A System for Automating Analog Layout. IEEE Des. Test Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2021	—	`conf`	Aging of Current DACs and its Impact in Equalizer Circuits. IRPS Tonmoy Dhar, Jitesh Poojary, Ramesh Harjani, Sachin S. Sapatnekar
2021	A	`conf`	Analog Layout Generation using Optimized Primitives. DATE Meghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani
2021	A	`conf`	Analytical Modeling of Transient Electromigration Stress based on Boundary Reflections. ICCAD Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestor E. Evmorfopoulos, Sachin S. Sapatnekar
2021	A	`conf`	BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology. ICCAD Vidya A. Chhabria, Kishor Kunal, Masoud Zabihi, Sachin S. Sapatnekar
2021	—	`conf`	CAMeleon: Reconfigurable B(T)CAM in Computational RAM. ACM Great Lakes Symposium on VLSI Zamshed I. Chowdhury, Salonik Resch, M. Hüsrev Cilasun, Zhengyang Zhao, Masoud Zabihi, Sachin S. Sapatnekar, Jianping Wang, Ulya R. Karpuzcu
2021	A	`conf`	Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. DATE Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar
2021	—	`conf`	DeepOpt: Optimized Scheduling of CNN Workloads for ASIC-based Systolic Deep Learning Accelerators. ASP-DAC Susmita Dey Manasi, Sachin S. Sapatnekar
2021	J	`jnl`	Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks. CoRR Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
2021	J	`jnl`	Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing Accelerator. CoRR Masoud Zabihi, Salonik Resch, M. Hüsrev Cilasun, Zamshed I. Chowdhury, Zhengyang Zhao, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar
2021	—	`conf`	Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. ASP-DAC Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2021	A	`conf`	From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen
2021	J	`jnl`	GNNIE: GNN Inference Engine with Load-balancing and Graph-Specific Caching. CoRR Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Sachin S. Sapatnekar
2021	A	`conf`	MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification. DATE Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar
2021	—	`conf`	Machine Learning Techniques in Analog Layout Automation. ISPD Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2021	J	`jnl`	OpeNPDN: A Neural-network-based Framework for Power Delivery Network Synthesis. CoRR Vidya A. Chhabria, Sachin S. Sapatnekar
2021	A	`conf`	Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. ICCAD Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar
2021	J	`jnl`	SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using Optimized Thresholds. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Farhana Sharmin Snigdha, Susmita Dey Manasi, Jiang Hu, Sachin S. Sapatnekar
2021	—	`conf`	Seeds of SEED: H-CRAM: In-memory Homomorphic Search Accelerator using Spintronic Computational RAM. SEED M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2021	J	`jnl`	Spiking Neural Networks in Spintronic Computational RAM. ACM Trans. Archit. Code Optim. M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Keshab K. Parhi, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2021	—	`conf`	Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. ASP-DAC Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
2021	J	`jnl`	Towards Homomorphic Inference Beyond the Edge. CoRR Salonik Resch, Zamshed I. Chowdhury, M. Hüsrev Cilasun, Masoud Zabihi, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2021	A	`conf`	VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis. ICCAD Hadi Esmaeilzadeh, Soroush Ghodrati, Jie Gu, Shiyu Guo, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Rohan Mahapatra, Susmita Dey Manasi, Edwin Mascarenhas, Sachin S. Sapatnekar, Ravi Varadarajan, Zhiang Wang, Hanyang Xu, Brahmendra Reddy Yatham, Ziqing Zeng
2020	A	`conf`	A Customized Graph Neural Network Model for Guiding Analog IC Placement. ICCAD Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2020	A	`conf`	A general approach for identifying hierarchical symmetry constraints for analog circuit layout. ICCAD Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
2020	J	`jnl`	A general approach for identifying hierarchical symmetry constraints for analog circuit layout. CoRR Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
2020	J	`jnl`	ALIGN: A System for Automating Analog Layout. CoRR Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz
2020	J	`jnl`	Adaptive-Length Coding of Image Data for Low-Cost Approximate Storage. IEEE Trans. Computers Qianqian Fan, David J. Lilja, Sachin S. Sapatnekar
2020	J	`jnl`	An Inference and Learning Engine for Spiking Neural Networks in Computational RAM (CRAM). CoRR M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Keshab K. Parhi, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2020	A*	`conf`	CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAM. DAC M. Hüsrev Cilasun, Salonik Resch, Zamshed Iqbal Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2020	—	`conf`	Exploring a Machine Learning Approach to Performance Driven Analog IC Placement. ISVLSI Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2020	A	`conf`	GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2020	—	`conf`	Learning from Experience: Applying ML to Analog Circuit Design. ISPD Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar
2020	J	`jnl`	MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification. CoRR Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar
2020	A*	`conf`	MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications. MICRO Salonik Resch, S. Karen Khatamifard, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, M. Hüsrev Cilasun, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2020	J	`jnl`	NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients. IEEE Trans. Very Large Scale Integr. Syst. Susmita Dey Manasi, Farhana Sharmin Snigdha, Sachin S. Sapatnekar
2020	J	`jnl`	PIMBALL: Binary Neural Networks in Spintronic Memory. ACM Trans. Archit. Code Optim. Salonik Resch, S. Karen Khatamifard, Zamshed Iqbal Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2020	—	`conf`	Stress-Induced Performance Shifts in Flexible System-in-Foils Using Ultra-Thin Chips. ISQED Tengtao Li, Sachin S. Sapatnekar
2020	—	`conf`	Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques. ASP-DAC Vidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatnekar, Bangqi Xu
2020	A	`conf`	The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2020	J	`jnl`	Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. CoRR Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
2019	—	`conf`	A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control. ISSCC Luke R. Everson, Sachin S. Sapatnekar, Chris H. Kim
2019	J	`jnl`	A Machine Learning Accelerator In-Memory for Energy Harvesting. CoRR Salonik Resch, S. Karen Khatamifard, Zamshed Iqbal Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2019	A*	`conf`	ALIGN: Open-Source Analog Layout Automation from the Ground Up. DAC Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar
2019	J	`jnl`	An Analytical Approach for Error PMF Characterization in Approximate Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar
2019	A	`conf`	An Energy Efficient Non-Volatile Flip-Flop based on CoMET Technology. DATE Robert Perricone, Zhaoxin Liang, Meghna G. Mankalale, Michael T. Niemier, Sachin S. Sapatnekar, Jianping Wang, Xiaobo Sharon Hu
2019	J	`jnl`	Dynamic Approximation of JPEG Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar
2019	—	`conf`	Electromigration-Aware Interconnect Design. ISPD Sachin S. Sapatnekar
2019	—	`ch.`	Error Analysis and Optimization in Approximate Arithmetic Circuits. Approximate Circuits Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar
2019	—	`conf`	Fast Mapping-Based High-Level Synthesis of Pipelined Circuits. ISQED Chaofan Li, Sachin S. Sapatnekar, Jiang Hu
2019	—	`conf`	Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs. ISQED Vidya A. Chhabria, Sachin S. Sapatnekar
2019	B	`conf`	Improving QoS for Global Dual-Criticality Scheduling on Multiprocessors. RTCSA Lin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu
2019	J	`jnl`	In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping. IEEE Trans. Computers Masoud Zabihi, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar
2019	J	`jnl`	NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients. CoRR Susmita Dey Manasi, Farhana Sharmin Snigdha, Sachin S. Sapatnekar
2019	—	`conf`	Reliability Analysis of a Delay-Locked Loop Under HCI and BTI Degradation. IRPS Tonmoy Dhar, Sachin S. Sapatnekar
2019	—	`conf`	SeFAct: selective feature activation and early classification for CNNs. ASP-DAC Farhana Sharmin Snigdha, Ibrahim Ahmed, Susmita Dey Manasi, Meghna G. Mankalale, Jiang Hu, Sachin S. Sapatnekar
2019	J	`jnl`	Stress-Induced Performance Shifts in 3D DRAMs. ACM Trans. Design Autom. Electr. Syst. Tengtao Li, Sachin S. Sapatnekar
2019	A*	`conf`	Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. DAC Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu
2019	—	`conf`	True In-memory Computing with the CRAM: From Technology to Applications. ACM Great Lakes Symposium on VLSI Masoud Zabihi, Zhengyang Zhao, Zamshed I. Chowdhury, Salonik Resch, Mahendra DC, Thomas Peterson, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar
2019	C	`conf`	Using DCT-based Approximate Communication to Improve MPI Performance in Parallel Clusters. IPCCC Qianqian Fan, David J. Lilja, Sachin S. Sapatnekar
2019	—	`conf`	Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform. ISQED Masoud Zabihi, Zhengyang Zhao, D. C. Mahendra, Zamshed I. Chowdhury, Salonik Resch, Thomas Peterson, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar
2018	J	`jnl`	A Simple Yet Efficient Accuracy-Configurable Adder Design. IEEE Trans. Very Large Scale Integr. Syst. Wenbin Xu, Sachin S. Sapatnekar, Jiang Hu
2018	J	`jnl`	Circuit Performance Shifts Due to Layout-Dependent Stress in Planar and 3D-ICs. IEEE Trans. Very Large Scale Integr. Syst. Sravan K. Marella, Sachin S. Sapatnekar
2018	J	`jnl`	Computational RAM to Accelerate String Matching at Scale. CoRR Zamshed I. Chowdhury, S. Karen Khatamifard, Zhengyang Zhao, Masoud Zabihi, Salonik Resch, Meisam Razaviyayn, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2018	A	`conf`	Computing-in-memory with spintronics. DATE Shubham Jain, Sachin S. Sapatnekar, Jianping Wang, Kaushik Roy, Anand Raghunathan
2018	J	`jnl`	Efficient In-Memory Processing Using Spintronics. IEEE Comput. Archit. Lett. Zamshed I. Chowdhury, Jonathan D. Harms, S. Karen Khatamifard, Masoud Zabihi, Yang Lv, Andrew Lyle, Sachin S. Sapatnekar, Ulya R. Karpuzcu, Jianping Wang
2018	J	`jnl`	Exploiting Processing in Non-Volatile Memory for Binary Neural Network Accelerators. CoRR Salonik Resch, S. Karen Khatamifard, Zamshed Iqbal Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
2018	Misc	`conf`	Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems. RTNS Lin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu
2018	—	`conf`	Plenaries. SMACD Marcel Urban, Sachin S. Sapatnekar, Richard Shi
2018	J	`jnl`	SkyLogic - A proposal for a skyrmion logic device. CoRR Meghna G. Mankalale, Zhengyang Zhao, Jianping Wang, Sachin S. Sapatnekar
2018	A	`conf`	Strain-aware performance evaluation and correction for OTFT-based flexible displays. ICCAD Tengtao Li, Sachin S. Sapatnekar
2018	A*	`conf`	Using imprecise computing for improved non-preemptive real-time scheduling. DAC Lin Huang, Youmeng Li, Sachin S. Sapatnekar, Jiang Hu
2017	A*	`conf`	A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. DAC Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami
2017	Misc	`conf`	A quantifiable approach to approximate computing: special session. CASES Chaofan Li, Deepashree Sengupta, Farhana Sharmin Snigdha, Wenbin Xu, Jiang Hu, Sachin S. Sapatnekar
2017	A	`conf`	A simple yet efficient accuracy configurable adder design. ISLPED Wenbin Xu, Sachin S. Sapatnekar, Jiang Hu
2017	A	`conf`	Advanced spintronic memory and logic for non-volatile processors. DATE Robert Perricone, Ibrahim Ahmed, Zhaoxin Liang, Meghna G. Mankalale, Xiaobo Sharon Hu, Chris H. Kim, Michael T. Niemier, Sachin S. Sapatnekar, Jianping Wang
2017	—	`conf`	Cost-quality trade-offs of approximate memory repair mechanisms for image data. ISQED Qianqian Fan, Sachin S. Sapatnekar, David J. Lilja
2017	J	`jnl`	Estimating Circuit Aging Due to BTI and HCI Using Ring-Oscillator-Based Sensors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Deepashree Sengupta, Sachin S. Sapatnekar
2017	J	`jnl`	Fast Stochastic Analysis of Electromigration in Power Distribution Networks. IEEE Trans. Very Large Scale Integr. Syst. Palkesh Jain, Vivek Mishra, Sachin S. Sapatnekar
2017	A*	`conf`	Incorporating the Role of Stress on Electromigration in Power Grids with Via Arrays. DAC Vivek Mishra, Palkesh Jain, Sravan K. Marella, Sachin S. Sapatnekar
2017	J	`jnl`	Probabilistic Wire Resistance Degradation Due to Electromigration in Power Grids. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vivek Mishra, Sachin S. Sapatnekar
2017	A*	`conf`	SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits. DAC Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar
2017	A	`conf`	Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs. ICCAD Tengtao Li, Sachin S. Sapatnekar
2016	J	`jnl`	A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects. IEEE Trans. Very Large Scale Integr. Syst. Palkesh Jain, Jordi Cortadella, Sachin S. Sapatnekar
2016	J	`jnl`	Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
2016	J	`jnl`	CoMET: Composite-Input Magnetoelectric-based Logic Technology. CoRR Meghna G. Mankalale, Zhaoxin Liang, Zhengyang Zhao, Chris H. Kim, Jianping Wang, Sachin S. Sapatnekar
2016	A	`conf`	Control synthesis and delay sensor deployment for efficient ASV designs. ICCAD Chaofan Li, Sachin S. Sapatnekar, Jiang Hu
2016	A*	`conf`	Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture. DAC Deepashree Sengupta, Vivek Mishra, Sachin S. Sapatnekar
2016	—	`conf`	Logic and memory design using spin-based circuits. ASP-DAC Zhaoxin Liang, Meghna G. Mankalale, Brandon Del Bel, Sachin S. Sapatnekar
2016	A*	`conf`	Optimal design of JPEG hardware under the approximate computing paradigm. DAC Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar
2016	J	`jnl`	Optimized Standard Cells for All-Spin Logic. ACM J. Emerg. Technol. Comput. Syst. Meghna G. Mankalale, Sachin S. Sapatnekar
2016	—	`ch.`	Power Grid Analysis. Encyclopedia of Algorithms Sachin S. Sapatnekar
2016	A*	`conf`	Predicting electromigration mortality under temperature and product lifetime specifications. DAC Vivek Mishra, Sachin S. Sapatnekar
2016	—	`conf`	Ring Oscillator Clocks and Margins. ASYNC Jordi Cortadella, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar
2016	J	`jnl`	STEM: A Scheme for Two-phase Evaluation of Majority Logic. CoRR Meghna G. Mankalale, Zhaoxin Liang, Sachin S. Sapatnekar
2016	—	`ch.`	Statistical Timing Analysis. Encyclopedia of Algorithms Sachin S. Sapatnekar
2015	J	`jnl`	A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations. IEEE Trans. Very Large Scale Integr. Syst. Sravan K. Marella, Sachin S. Sapatnekar
2015	—	`conf`	A retargetable and accurate methodology for logic-IP-internal electromigration assessment. ASP-DAC Palkesh Jain, Sachin S. Sapatnekar, Jordi Cortadella
2015	—	`conf`	Circuit delay variability due to wire resistance evolution under AC electromigration. IRPS Vivek Mishra, Sachin S. Sapatnekar
2015	A	`conf`	FEMTO: Fast Error Analysis in Multipliers through Topological Traversal. ICCAD Deepashree Sengupta, Sachin S. Sapatnekar
2015	—	`conf`	Impact on performance, power, area and wirelength using electromigration-aware cells. ICECS Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
2015	A*	`conf`	Joint precision optimization and high level synthesis for approximate computing. DAC Chaofan Li, Wei Luo, Sachin S. Sapatnekar, Jiang Hu
2015	A	`conf`	Optimization of FinFET-based circuits using a dual gate pitch technique. ICCAD Sravan K. Marella, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Sachin S. Sapatnekar
2015	J	`jnl`	RTL Synthesis: From Logic Synthesis to Automatic Pipelining. Proc. IEEE Jordi Cortadella, Marc Galceran Oms, Michael Kishinevsky, Sachin S. Sapatnekar
2015	C	`conf`	Reactive clocks with variability-tracking jitter. ICCD Jordi Cortadella, Luciano Lavagno, Pedro Lopez, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar
2015	—	`conf`	Reducing the signal Electromigration effects on different logic gates by cell layout optimization. LASCAS Gracieli Posser, Lucas de Paris, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
2015	J	`jnl`	Spin-Based Computing: Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor. Proc. IEEE Jongyeon Kim, Ayan Paul, Paul A. Crowell, Steven J. Koester, Sachin S. Sapatnekar, Jianping Wang, Chris H. Kim
2015	—	`conf`	Stochastic and topologically aware electromigration analysis for clock skew. IRPS Palkesh Jain, Sachin S. Sapatnekar, Jordi Cortadella
2014	A	`conf`	A systematic approach for analyzing and optimizing cell-internal signal electromigration. ICCAD Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
2014	—	`conf`	Analyzing the electromigration effects on different metal layers and different wire lengths. ICECS Gracieli Posser, Vivek Mishra, Ricardo Augusto da Luz Reis, Sachin S. Sapatnekar
2014	J	`jnl`	Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. Pingqiang Zhou, Ayan Paul, Chris H. Kim, Sachin S. Sapatnekar
2014	A	`conf`	Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems. IPDPS Jieming Yin, Pingqiang Zhou, Sachin S. Sapatnekar, Antonia Zhai
2014	A	`conf`	Improving STT-MRAM density through multibit error correction. DATE Brandon Del Bel, Jongyeon Kim, Chris H. Kim, Sachin S. Sapatnekar
2014	J	`jnl`	Incorporating Hot-Carrier Injection Effects Into Timing Analysis for Large Circuits. IEEE Trans. Very Large Scale Integr. Syst. Jianxin Fang, Sachin S. Sapatnekar
2014	J	`jnl`	Incremental Analysis of Power Grids Using Backward Random Walks. ACM Trans. Design Autom. Electr. Syst. Baktash Boghrati, Sachin S. Sapatnekar
2014	Misc	`conf`	Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations. VLSID Ayan Paul, Chaitanya Kshirsagar, Sachin S. Sapatnekar, Steven J. Koester, Chris H. Kim
2014	—	`conf`	Predicting circuit aging using ring oscillators. ASP-DAC Deepashree Sengupta, Sachin S. Sapatnekar
2014	A	`conf`	ReSCALE: recalibrating sensor circuits for aging and lifetime estimation under BTI. ICCAD Deepashree Sengupta, Sachin S. Sapatnekar
2014	J	`jnl`	Techniques for scalable and effective routability evaluation. ACM Trans. Design Autom. Electr. Syst. Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
2014	J	`jnl`	Variation-Aware Variable Latency Design. IEEE Trans. Very Large Scale Integr. Syst. Saket Gupta, Sachin S. Sapatnekar
2013	A	`conf`	CATALYST: planning layer directives for effective design closure. DATE Yaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar
2013	J	`jnl`	Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sachin S. Sapatnekar
2013	J	`jnl`	Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sachin S. Sapatnekar
2013	J	`jnl`	Employing circadian rhythms to enhance power and reliability. ACM Trans. Design Autom. Electr. Syst. Saket Gupta, Sachin S. Sapatnekar
2013	A	`conf`	Placement optimization of power supply pads based on locality. DATE Pingqiang Zhou, Vivek Mishra, Sachin S. Sapatnekar
2013	A*	`conf`	The impact of electromigration in copper interconnects on power grid integrity. DAC Vivek Mishra, Sachin S. Sapatnekar
2013	A	`conf`	The impact of shallow trench isolation effects on circuit performance. ICCAD Sravan K. Marella, Sachin S. Sapatnekar
2013	—	`conf`	What happens when circuits grow old: Aging issues in CMOS design. VLSI-DAT Sachin S. Sapatnekar
2012	A	`conf`	A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations. ICCAD Sravan K. Marella, Sanjay V. Kumar, Sachin S. Sapatnekar
2012	—	`conf`	BTI-aware design using variable latency units. ASP-DAC Saket Gupta, Sachin S. Sapatnekar
2012	A	`conf`	Circuit reliability: From Physics to Architectures: Embedded tutorial paper. ICCAD Jianxin Fang, Saket Gupta, Sanjay V. Kumar, Sravan K. Marella, Vivek Mishra, Pingqiang Zhou, Sachin S. Sapatnekar
2012	J	`jnl`	Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations. IEEE Trans. Very Large Scale Integr. Syst. Saket Gupta, Sachin S. Sapatnekar
2012	J	`jnl`	Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sachin S. Sapatnekar
2012	A	`conf`	Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems. ISLPED Jieming Yin, Pingqiang Zhou, Anup Holey, Sachin S. Sapatnekar, Antonia Zhai
2012	J	`jnl`	Fast poisson solvers for thermal analysis. ACM Trans. Design Autom. Electr. Syst. Haifeng Qian, Sachin S. Sapatnekar, Eren Kursun
2012	A*	`conf`	GLARE: global and local wiring aware routability evaluation. DAC Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar
2012	—	`conf`	GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation. ASP-DAC Saket Gupta, Sachin S. Sapatnekar
2012	—	`conf`	Incremental power network analysis using backward random walks. ASP-DAC Baktash Boghrati, Sachin S. Sapatnekar
2012	A	`conf`	Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications. ICCAD Pingqiang Zhou, Won Ho Choi, Bongjin Kim, Chris H. Kim, Sachin S. Sapatnekar
2012	J	`jnl`	Optimized 3D Network-on-Chip Design Using Simulated Allocation. ACM Trans. Design Autom. Electr. Syst. Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar
2012	J	`jnl`	Process and Reliability Sensors for Nanoscale CMOS. IEEE Des. Test Comput. John Keane, Chris H. Kim, Qunzeng Liu, Sachin S. Sapatnekar
2012	—	`conf`	Residential task scheduling under dynamic pricing using the multiple knapsack method. ISGT N. Kumaraguruparan, H. Sivaramakrishnan, Sachin S. Sapatnekar
2012	J	`jnl`	Scalable Methods for Analyzing the Circuit Failure Probability Due to Gate Oxide Breakdown. IEEE Trans. Very Large Scale Integr. Syst. Jianxin Fang, Sachin S. Sapatnekar
2012	—	`conf`	Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors. CICC Ayan Paul, Matt Amrein, Saket Gupta, Arvind Vinod, Abhishek Arun, Sachin S. Sapatnekar, Chris H. Kim
2012	—	`conf`	The impact of hot carriers on timing in large circuits. ASP-DAC Jianxin Fang, Sachin S. Sapatnekar
2011	A	`conf`	A scaled random walk solver for fast power grid analysis. DATE Baktash Boghrati, Sachin S. Sapatnekar
2011	—	`conf`	Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability. ASP-DAC Jianxin Fang, Sachin S. Sapatnekar
2011	J	`jnl`	Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2011	J	`jnl`	Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sachin S. Sapatnekar
2011	A	`conf`	Enabling improved power management in multicore processors through clustered DVFS. DATE T. Kolpe, Antonia Zhai, Sachin S. Sapatnekar
2011	—	`conf`	Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network. CICC Pingqiang Zhou, Dong Jiao, Chris H. Kim, Sachin S. Sapatnekar
2011	A	`conf`	NoC frequency scaling with flexible-pipeline routers. ISLPED Pingqiang Zhou, Jieming Yin, Antonia Zhai, Sachin S. Sapatnekar
2011	J	`jnl`	Overcoming Variations in Nanometer-Scale Technologies. IEEE J. Emerg. Sel. Topics Circuits Syst. Sachin S. Sapatnekar
2011	—	`ch.`	Statistical Design of Integrated Circuits. Low-Power Variation-Tolerant Design in Nanometer Silicon Sachin S. Sapatnekar
2011	A	`conf`	The whys and hows of thermal management. ISLPED Sachin S. Sapatnekar
2011	A*	`conf`	Thermal signature: a simple yet accurate thermal index for floorplan optimization. DAC Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin
2010	—	`conf`	Adding a new dimension to physical design. ISPD Sachin S. Sapatnekar
2010	—	`conf`	Application-specific 3D Network-on-Chip design using simulated allocation. ASP-DAC Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar
2010	J	`jnl`	Capturing Post-Silicon Variations Using a Representative Critical Path. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qunzeng Liu, Sachin S. Sapatnekar
2010	—	`conf`	Current source modeling in the presence of body bias. ASP-DAC Saket Gupta, Sachin S. Sapatnekar
2010	—	`conf`	Dummy fill optimization for enhanced manufacturability. ISPD Yaoguang Wei, Sachin S. Sapatnekar
2010	J	`jnl`	Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sachin S. Sapatnekar
2010	A	`conf`	Fast Poisson solvers for thermal analysis. ICCAD Haifeng Qian, Sachin S. Sapatnekar
2010	—	`conf`	Incremental solution of power grids using random walks. ASP-DAC Baktash Boghrati, Sachin S. Sapatnekar
2010	—	`conf`	Physical design techniques for optimizing RTA-induced variations. ASP-DAC Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar
2010	A*	`ed.`	Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010 DAC Sachin S. Sapatnekar
2010	—	`conf`	Scalable methods for the analysis and optimization of gate oxide breakdown. ISQED Jianxin Fang, Sachin S. Sapatnekar
2009	J	`jnl`	A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qunzeng Liu, Sachin S. Sapatnekar
2009	J	`jnl`	A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang
2009	—	`conf`	Adaptive techniques for overcoming performance degradation due to aging in digital circuits. ASP-DAC Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2009	—	`conf`	Addressing thermal and power delivery bottlenecks in 3D circuits. ASP-DAC Sachin S. Sapatnekar
2009	—	`conf`	Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors. ASP-DAC Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar
2009	J	`jnl`	Fast and Accurate Statistical Criticality Computation Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan
2009	J	`jnl`	Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity. IEEE Des. Test Comput. Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar
2009	—	`conf`	Synthesizing a representative critical path for post-silicon delay prediction. ISPD Qunzeng Liu, Sachin S. Sapatnekar
2009	J	`jnl`	Technical perspective - Where the chips may fall. Commun. ACM Sachin S. Sapatnekar
2008	J	`jnl`	A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar
2008	J	`jnl`	A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaskirat Singh, Sachin S. Sapatnekar
2008	A*	`conf`	A framework for block-based timing sensitivity analysis. DAC Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar
2008	A*	`conf`	A progressive-ILP based routing algorithm for cross-referencing biochips. DAC Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang
2008	J	`jnl`	Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)]. IEEE Des. Test Comput. Sachin S. Sapatnekar
2008	J	`jnl`	Automated module assignment in stacked-Vdd designs for high-efficiency power delivery. ACM J. Emerg. Technol. Comput. Syst. Yong Zhan, Sachin S. Sapatnekar
2008	J	`jnl`	Body Bias Voltage Computations for Process and Temperature Compensation. IEEE Trans. Very Large Scale Integr. Syst. Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2008	J	`jnl`	Buffering global interconnects in structured ASIC design. Integr. Tianpei Zhang, Sachin S. Sapatnekar
2008	J	`jnl`	Building your yield of dreams. IEEE Des. Test Comput. Sachin S. Sapatnekar
2008	—	`book`	Handbook of Algorithms for Physical Design Automation. Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar
2008	—	`ch.`	Introduction to Physical Design. Handbook of Algorithms for Physical Design Automation Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar
2008	—	`ch.`	Metrics Used in Physical Design. Handbook of Algorithms for Physical Design Automation Frank Liu, Sachin S. Sapatnekar
2008	—	`ch.`	Physical Design for Three-Dimensional Circuits. Handbook of Algorithms for Physical Design Automation Kia Bazargan, Sachin S. Sapatnekar
2008	A*	`conf`	Reinventing EDA with manycore processors. DAC Sachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou
2008	J	`jnl`	Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim
2008	J	`jnl`	Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. IEEE Trans. Very Large Scale Integr. Syst. Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim
2008	J	`jnl`	Stochastic Preconditioning for Diagonally Dominant Matrices. SIAM J. Sci. Comput. Haifeng Qian, Sachin S. Sapatnekar
2008	J	`jnl`	Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shrirang K. Karandikar, Sachin S. Sapatnekar
2008	J	`jnl`	Thermally Aware Design. Found. Trends Electron. Des. Autom. Yong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar
2008	J	`jnl`	Variability and Statistical Design. IPSJ Trans. Syst. LSI Des. Methodol. Sachin S. Sapatnekar
2007	A	`conf`	A general model for performance optimization of sequential systems. ICCAD Dmitry Bufistov, Jordi Cortadella, Michael Kishinevsky, Sachin S. Sapatnekar
2007	J	`jnl`	Book Review: An Assay of Biochips. IEEE Des. Test Comput. Sachin S. Sapatnekar
2007	A	`conf`	Clustering based pruning for statistical criticality computation under process variations. ICCAD Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan
2007	—	`conf`	Computer-aided design of 3d integrated circuits. ACM Great Lakes Symposium on VLSI Sachin S. Sapatnekar
2007	A*	`conf`	Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations. DAC Qunzeng Liu, Sachin S. Sapatnekar
2007	J	`jnl`	DAC Highlights. IEEE Des. Test Comput. Sachin S. Sapatnekar, Leon Stok
2007	—	`conf`	DAG based library-free technology mapping. ACM Great Lakes Symposium on VLSI Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
2007	J	`jnl`	Editorial to special issue DAC 2006. ACM J. Emerg. Technol. Comput. Syst. Krishnendu Chakrabarty, Sachin S. Sapatnekar
2007	J	`jnl`	High-Efficiency Green Function-Based Thermal Simulation Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yong Zhan, Sachin S. Sapatnekar
2007	J	`jnl`	In Memoriam: Margarida F. Jacome. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gustavo de Veciana, Marcello Lajolo, Chen He, Enrico Macii, Sachin S. Sapatnekar
2007	A	`conf`	Module assignment for pin-limited designs under the stacked-Vdd paradigm. ICCAD Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar
2007	A*	`conf`	NBTI-Aware Synthesis of Digital Circuits. DAC Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2007	A*	`conf`	Placement of 3D ICs with Thermal and Interlayer Via Considerations. DAC Brent Goplen, Sachin S. Sapatnekar
2007	J	`jnl`	Prediction of leakage power under process uncertainties. ACM Trans. Design Autom. Electr. Syst. Hongliang Chang, Sachin S. Sapatnekar
2007	—	`conf`	Probabilistic Congestion Prediction with Partial Blockages. ISQED Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi
2007	—	`book`	Routing Congestion in VLSI Circuits - Estimation and Optimization. Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar
2007	J	`jnl`	Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. IEEE Trans. Very Large Scale Integr. Syst. Tianpei Zhang, Sachin S. Sapatnekar
2007	A*	`conf`	Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. DAC Jie Gu, Sachin S. Sapatnekar, Chris H. Kim
2006	—	`conf`	A fixed-die floorplanning algorithm using an analytical approach. ASP-DAC Yong Zhan, Yan Feng, Sachin S. Sapatnekar
2006	J	`jnl`	Accurate estimation of global buffer delay within a floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
2006	A	`conf`	An analytical model for negative bias temperature instability. ICCAD Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2006	J	`jnl`	Book Reviews: Plumbing the Depths of Leakage. IEEE Des. Test Comput. Sachin S. Sapatnekar
2006	B	`conf`	Comparing simulation techniques for microarchitecture-aware floorplanning. ISPASS Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar
2006	J	`jnl`	DAC Highlights. IEEE Des. Test Comput. Sachin S. Sapatnekar, Grant Martin
2006	—	`conf`	Electrothermal analysis and optimization techniques for nanoscale integrated circuits. ASP-DAC Yong Zhan, Brent Goplen, Sachin S. Sapatnekar
2006	—	`conf`	Fast disjoint transistor networks from BDDs. SBCCI Leomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
2006	—	`conf`	Impact of NBTI on SRAM Read Stability and Design for Reliability. ISQED Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2006	—	`conf`	Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. ASP-DAC Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2006	J	`jnl`	Partition-Based Algorithm for Power Grid Design Using Locality. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaskirat Singh, Sachin S. Sapatnekar
2006	J	`jnl`	Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Brent Goplen, Sachin S. Sapatnekar
2006	A*	`conf`	Statistical timing analysis with correlated non-gaussian parameters using independent component analysis. DAC Jaskirat Singh, Sachin S. Sapatnekar
2006	A*	`conf`	Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. DAC John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim
2006	J	`jnl`	Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar
2006	J	`jnl`	Temperature-Aware Placement for SOCs. Proc. IEEE Jeng-Liang Tsai, Charlie Chung-Ping Chen, Guoqiang Chen, Brent Goplen, Haifeng Qian, Yong Zhan, Sung-Mo Kang, Martin D. F. Wong, Sachin S. Sapatnekar
2006	A	`conf`	Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. ISLPED Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar
2006	—	`conf`	Temperature-aware routing in 3D ICs. ASP-DAC Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar
2006	—	`conf`	Tutorial II: Variability and Its Impact on Design. ISQED Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar
2006	—	`conf`	Width Quantization Aware FinFET Circuit Design. CICC Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim
2005	—	`conf`	A fast algorithm for power grid design. ISPD Jaskirat Singh, Sachin S. Sapatnekar
2005	A	`conf`	A high efficiency full-chip thermal simulation algorithm. ICCAD Yong Zhan, Sachin S. Sapatnekar
2005	A	`conf`	A hybrid linear equation solver and its application in quadratic placement. ICCAD Haifeng Qian, Sachin S. Sapatnekar
2005	—	`conf`	A new approach to the use of satisfiability in false path detection. ACM Great Lakes Symposium on VLSI Felipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
2005	J	`jnl`	A predictive distributed congestion metric with application to technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
2005	J	`jnl`	An EDA compendium. IEEE Des. Test Comput. Sachin S. Sapatnekar
2005	—	`conf`	An efficient technology mapping algorithm targeting routing congestion under delay constraints. ISPD Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar
2005	J	`jnl`	BDD decomposition for delay oriented pass transistor logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. Rupesh S. Shelar, Sachin S. Sapatnekar
2005	—	`conf`	Buffering global interconnects in structured ASIC design. ASP-DAC Tianpei Zhang, Sachin S. Sapatnekar
2005	J	`jnl`	Congestion-aware topology optimization of structured power/ground networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaskirat Singh, Sachin S. Sapatnekar
2005	J	`jnl`	Designing "Vary" Good Circuitry. IEEE Des. Test Comput. Sachin S. Sapatnekar
2005	—	`conf`	Designing optimized pipelined global interconnects: algorithms and methodology impact. ISCAS (1) Vidyasagar Nookala, Sachin S. Sapatnekar
2005	J	`jnl`	Early-stage power grid analysis for uncertain working modes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
2005	J	`jnl`	Empowering the designer. IEEE Des. Test Comput. Sachin S. Sapatnekar
2005	C	`conf`	Exact lower bound for the number of switches in series to implement a combinational logic cell. ICCD Felipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
2005	J	`jnl`	Fast comparisons of circuit implementations. IEEE Trans. Very Large Scale Integr. Syst. Shrirang K. Karandikar, Sachin S. Sapatnekar
2005	—	`conf`	Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up. ASP-DAC Yong Zhan, Sachin S. Sapatnekar
2005	—	`conf`	Fast estimation of area-delay trade-offs in circuit sizing. ISCAS (4) Shrirang K. Karandikar, Sachin S. Sapatnekar
2005	A*	`conf`	Full-chip analysis of leakage power under process variations, including spatial correlations. DAC Hongliang Chang, Sachin S. Sapatnekar
2005	J	`jnl`	Gate oxide leakage and delay tradeoffs for dual-T IEEE Trans. Very Large Scale Integr. Syst. Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
2005	J	`jnl`	Guest Editors' Introduction: New Dimensions in 3D Integration. IEEE Des. Test Comput. Sachin S. Sapatnekar, Kevin J. Nowka
2005	Misc	`conf`	High-Speed Interconnect Technology: On-Chip and Off-Chip. VLSI Design Sachin S. Sapatnekar, Jaijeet S. Roychowdhury, Ramesh Harjani
2005	A*	`conf`	Microarchitecture-aware floorplanning using a statistical design of experiments approach. DAC Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar
2005	A*	`conf`	Net weighting to reduce repeater counts during placement. DAC Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar
2005	J	`jnl`	Placement and Routing in 3D Integrated Circuits. IEEE Des. Test Comput. Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar
2005	J	`jnl`	Power grid analysis using random walks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
2005	A*	`conf`	Robust gate sizing by geometric programming. DAC Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar
2005	J	`jnl`	Statistical timing analysis under spatial correlations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hongliang Chang, Sachin S. Sapatnekar
2005	—	`conf`	Thermal via placement in 3D ICs. ISPD Brent Goplen, Sachin S. Sapatnekar
2004	A	`conf`	A chip-level electrostatic discharge simulation strategy. ICCAD Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar
2004	A*	`conf`	A method for correcting the functionality of a wire-pipelined circuit. DAC Vidyasagar Nookala, Sachin S. Sapatnekar
2004	J	`jnl`	A methodology for the simultaneous design of supply and signal networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
2004	J	`jnl`	A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints. ACM Trans. Design Autom. Electr. Syst. Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
2004	—	`conf`	A predictive distributed congestion metric and its application to technology mapping. ISPD Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
2004	A	`conf`	Accurate estimation of global buffer delay within a floorplan. ICCAD Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
2004	—	`conf`	Early-stage power grid analysis for uncertain working modes. ISPD Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
2004	A	`conf`	Fast Comparisons of Circuit Implementations. DATE Shrirang K. Karandikar, Sachin S. Sapatnekar
2004	—	`conf`	Hierarchical random-walk algorithms for power grid analysis. ASP-DAC Haifeng Qian, Sachin S. Sapatnekar
2004	Misc	`conf`	High-Performance Power Grids For Nanometer Technologies. VLSI Design Sachin S. Sapatnekar
2004	A	`conf`	Logical effort based technology mapping. ICCAD Shrirang K. Karandikar, Sachin S. Sapatnekar
2004	—	`conf`	On the selection of on-chip inductors for the optimal VCO design. CICC Yong Zhan, Ramesh Harjani, Sachin S. Sapatnekar
2004	A	`conf`	Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming. DATE Yong Zhan, Sachin S. Sapatnekar
2004	C	`conf`	Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. ICCD Tianpei Zhang, Sachin S. Sapatnekar
2004	—	`conf`	The Certainty of Uncertainty: Randomness in Nanometer Design. PATMOS Hongliang Chang, Haifeng Qian, Sachin S. Sapatnekar
2004	—	`book`	Timing. Sachin S. Sapatnekar
2004	—	`conf`	Topology optimization of structured power/ground networks. ISPD Jaskirat Singh, Sachin S. Sapatnekar
2004	A*	`conf`	Tradeoffs between date oxide leakage and delay for dual T DAC Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
2004	C	`conf`	Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits. ICCD Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
2003	J	`jnl`	A practical methodology for early buffer and wire resource allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
2003	C	`conf`	An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk. ICCD Venkatesan Rajappan, Sachin S. Sapatnekar
2003	J	`jnl`	Analysis and Optimization of Power Grids. IEEE Des. Test Comput. Sachin S. Sapatnekar, Haihua Su
2003	J	`jnl`	Analysis and optimization of structured power/ground networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haihua Su, Kaushik Gala, Sachin S. Sapatnekar
2003	A	`conf`	Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach. ICCAD Brent Goplen, Sachin S. Sapatnekar
2003	J	`jnl`	Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
2003	J	`jnl`	Guest editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Sachin S. Sapatnekar
2003	J	`jnl`	Optimal decoupling capacitor sizing and placement for standard-cell layout designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif
2003	—	`conf`	Partition-driven standard cell thermal placement. ISPD Guoqiang Chen, Sachin S. Sapatnekar
2003	A*	`conf`	Random walks in a supply network. DAC Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
2003	A	`conf`	Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal. ICCAD Hongliang Chang, Sachin S. Sapatnekar
2003	—	`conf`	Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
2003	J	`jnl`	Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect. IEEE Trans. Very Large Scale Integr. Syst. Shrirang K. Karandikar, Sachin S. Sapatnekar
2002	A	`conf`	A precorrected-FFT method for simulating on-chip inductance. ICCAD Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
2002	J	`jnl`	A timing-constrained simultaneous global routing algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiang Hu, Sachin S. Sapatnekar
2002	—	`conf`	An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. ASP-DAC/VLSI Design Rupesh S. Shelar, Sachin S. Sapatnekar
2002	—	`conf`	An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts. ISPD Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif
2002	A*	`conf`	Congestion-driven codesign of power and signal networks. DAC Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
2002	—	`conf`	Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. IWLS Rupesh S. Shelar, Sachin S. Sapatnekar
2002	C	`conf`	Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques. ICCD Haitian Hu, Sachin S. Sapatnekar
2002	J	`jnl`	Efficient inductance extraction using circuit-aware techniques. IEEE Trans. Very Large Scale Integr. Syst. Haitian Hu, Sachin S. Sapatnekar
2002	J	`jnl`	Fast and exact transistor sizing based on iterative relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
2002	J	`jnl`	Hierarchical analysis of power distribution networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw
2002	J	`jnl`	Low-power clock distribution using multiple voltages and reduced swings. IEEE Trans. Very Large Scale Integr. Syst. Jatuchai Pangjun, Sachin S. Sapatnekar
2002	—	`conf`	Optimized pin assignment for lower routing congestion after floorplanning phase. SLIP Tianpei Zhang, Sachin S. Sapatnekar
2002	J	`jnl`	Performance Driven Global Routing Through Gradual Refinement. VLSI Design Jiang Hu, Sachin S. Sapatnekar
2002	J	`jnl`	Probability-driven routing in a datapath environment. Integr. Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert
2002	—	`ed.`	Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002 ISPD Sachin S. Sapatnekar, Massoud Pedram
2002	A	`conf`	Standby power optimization via transistor sizing and dual threshold voltage assignment. ICCAD Mahesh Ketkar, Sachin S. Sapatnekar
2002	J	`jnl`	Technology mapping algorithms for domino logic. ACM Trans. Design Autom. Electr. Syst. Min Zhao, Sachin S. Sapatnekar
2001	A*	`conf`	A New Structural Pattern Matching Algorithm for Technology Mapping. DAC Min Zhao, Sachin S. Sapatnekar
2001	A*	`conf`	A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
2001	J	`jnl`	A survey on multi-net global routing for integrated circuits. Integr. Jiang Hu, Sachin S. Sapatnekar
2001	—	`conf`	Buffered Steiner trees for difficult instances. ISPD Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
2001	—	`conf`	Circuit-aware on-chip inductance extraction. CICC Haitian Hu, Sachin S. Sapatnekar
2001	J	`jnl`	Exact and efficient crosstalk estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Martin Kuhlmann, Sachin S. Sapatnekar
2001	A	`conf`	Hybrid Structured Clock Network Construction. ICCAD Haihua Su, Sachin S. Sapatnekar
2001	Misc	`conf`	Optimization and Analysis Techniques for the Deep Submicron Regime. VLSI Design Noel Menezes, Sachin S. Sapatnekar
2001	C	`conf`	Performance Driven Global Routing Through Gradual Refinement. ICCD Jiang Hu, Sachin S. Sapatnekar
2001	—	`ed.`	Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001 ISPD Sachin S. Sapatnekar, Manfred Wiesel
2001	A	`conf`	Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. ICCAD Rupesh S. Shelar, Sachin S. Sapatnekar
2001	J	`jnl`	Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
2001	—	`conf`	Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
2001	A*	`conf`	Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. DAC Shrirang K. Karandikar, Sachin S. Sapatnekar
2001	J	`jnl`	Technology mapping for high-performance static CMOS and pass transistor logic designs. IEEE Trans. Very Large Scale Integr. Syst. Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji
2000	A	`conf`	A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. ICCAD Jiang Hu, Sachin S. Sapatnekar
2000	J	`jnl`	A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar
2000	J	`jnl`	A timing model incorporating the effect of crosstalk on delay andits application to optimal channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sachin S. Sapatnekar
2000	J	`jnl`	Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiang Hu, Sachin S. Sapatnekar
2000	Misc	`conf`	Capturing the Effect of Crosstalk on Delay. VLSI Design Sachin S. Sapatnekar
2000	A*	`conf`	Convex delay models for transistor sizing. DAC Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar
2000	—	`conf`	Datapath routing based on a decongestion metric. ISPD Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert
2000	C	`conf`	Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic. ISCAS Min Zhao, Sachin S. Sapatnekar
2000	A	`conf`	Fast Analysis and Optimization of Power/Ground Networks. ICCAD Haihua Su, Kaushik Gala, Sachin S. Sapatnekar
2000	A*	`conf`	Hierarchical analysis of power distribution networks. DAC Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw
2000	A*	`conf`	MINFLOTRANSIT: min-cost flow based transistor sizing tool. DAC Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
2000	J	`jnl`	Power-delay optimizations in gate sizing. ACM Trans. Design Autom. Electr. Syst. Sachin S. Sapatnekar, Weitong Chuang
2000	J	`jnl`	Timing-driven partitioning and timing optimization of mixedstatic-domino implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Min Zhao, Sachin S. Sapatnekar
1999	A	`conf`	An integrated algorithm for combined placement and libraryless technology mapping. ICCAD Yanbin Jiang, Sachin S. Sapatnekar
1999	A	`conf`	Clock distribution using multiple voltages. ISLPED Jatuchai Pangjun, Sachin S. Sapatnekar
1999	C	`conf`	Efficient Crosstalk Estimation. ICCD Martin Kuhlmann, Sachin S. Sapatnekar, Keshab K. Parhi
1999	A*	`conf`	FAR-DS: Full-Plane AWE Routing with Driver Sizing. DAC Jiang Hu, Sachin S. Sapatnekar
1999	A	`conf`	Marsh: min-area retiming with setup and hold constraints. ICCAD Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
1999	J	`jnl`	Non-Hanan routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Huibo Hou, Jiang Hu, Sachin S. Sapatnekar
1999	J	`jnl`	Optimizing large multiphase level-clocked circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Naresh Maheshwari, Sachin S. Sapatnekar
1999	J	`jnl`	Retiming control logic. Integr. Naresh Maheshwari, Sachin S. Sapatnekar
1999	—	`conf`	Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. ISPD Jiang Hu, Sachin S. Sapatnekar
1999	A	`conf`	Timing-driven partitioning for two-phase domino and mixed static/domino implementations. ICCAD Min Zhao, Sachin S. Sapatnekar
1998	C	`conf`	A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic. ICCD Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji
1998	—	`conf`	Combined transistor sizing with buffer insertion for timing optimization. CICC Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim
1998	A	`conf`	Efficient Minarea Retiming of Large Level-Clocked Circuits. DATE Naresh Maheshwari, Sachin S. Sapatnekar
1998	J	`jnl`	Efficient retiming of large circuits. IEEE Trans. Very Large Scale Integr. Syst. Naresh Maheshwari, Sachin S. Sapatnekar
1998	J	`jnl`	Interleaving buffer insertion and transistor sizing into a single optimization. IEEE Trans. Very Large Scale Integr. Syst. Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim
1998	—	`conf`	Routing tree topology construction to meet interconnect timing constraints. ISPD Huibo Hou, Sachin S. Sapatnekar
1998	J	`jnl`	Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn
1998	A	`conf`	Technology mapping for domino logic. ICCAD Min Zhao, Sachin S. Sapatnekar
1997	J	`jnl`	A Framework for Exploiting Task and Data Parallelism on Distributed Memory Multicomputers. IEEE Trans. Parallel Distributed Syst. Shankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee
1997	A*	`conf`	An Improved Algorithm for Minimum-Area Retiming. DAC Naresh Maheshwari, Sachin S. Sapatnekar
1997	—	`conf`	Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. ISPD Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar
1997	A	`conf`	Minimum area retiming with equivalent initial states. ICCAD Naresh Maheshwari, Sachin S. Sapatnekar
1996	C	`conf`	A Practical Algorithm for Retiming Level-Clocked Circuits. ICCD Naresh Maheshwari, Sachin S. Sapatnekar
1996	A	`conf`	Clock tree synthesis for multi-chip modules. ICCAD Daksh Lehther, Sachin S. Sapatnekar
1996	J	`jnl`	Optimal design of macrocells for low power and high speed. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Piyush K. Sancheti, Sachin S. Sapatnekar
1996	J	`jnl`	Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sachin S. Sapatnekar, Rahul B. Deokar
1996	J	`jnl`	Wire sizing as a convex optimization problem: exploring the area-delay tradeoff. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sachin S. Sapatnekar
1996	Misc	`conf`	Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs. VLSI Design Jatan C. Shah, Sachin S. Sapatnekar
1995	A*	`conf`	A Fresh Look at Retiming Via Clock Skew Optimization. DAC Rahul B. Deokar, Sachin S. Sapatnekar
1995	C	`conf`	Layout Optimization Using Arbitrarily High Degree Posynomial Models. ISCAS Piyush K. Sancheti, Sachin S. Sapatnekar
1995	A	`conf`	Power vs. delay in gate sizing: conflicting objectives? ICCAD Sachin S. Sapatnekar, Weitong Chuang
1995	A	`conf`	Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. ICCAD Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn
1995	J	`jnl`	Timing and area optimization for standard-cell VLSI circuit design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj
1994	—	`conf`	A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers. ICPP (2) Shankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee
1994	C	`conf`	A Graph-Theoretic Approach to Clock Skew Optimization. ISCAS Rahul B. Deokar, Sachin S. Sapatnekar
1994	J	`jnl`	Convexity-based algorithms for design centering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang
1994	C	`conf`	High Performance CMOS Macromodule Layout Synthesis. ISCAS Jaewon Kim, Sung-Mo Kang, Sachin S. Sapatnekar
1994	A*	`conf`	RC Interconnect Optimization Under the Elmore Delay Model. DAC Sachin S. Sapatnekar
1993	A	`conf`	A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. ICCAD Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj
1993	J	`jnl`	An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang
1993	A	`conf`	Convexity-based algorithms for design centering. ICCAD Sachin S. Sapatnekar, Pravin M. Vaidya, Steve M. Kang
1993	C	`conf`	Feasible Region Approximation Using Convex Polytopes. ISCAS Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang
1992	—	`—`	A Convex Programming Approach to Problems in VLSI Design Sachin S. Sapatnekar
1991	A	`conf`	A Convex Optimization Approach to Transistor Sizing for CMOS Circuits. ICCAD Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya