Sachin Maheshwari

30 papers A 1C 4Journal 15Unranked 10
YearRankTypeTitle / Venue / Authors
2025 — conf
Dealing with Non-Idealities of Power-Clock Generation for Adiabatic Systems.
ICECS
Himadri Singh Raghav, Sachin Maheshwari, Mike Smart, Themis Prodromakis, Alexander Serb
2025 C conf
Low Offset, High-Resolution Threshold Logic Design in 22nm FDSOI.
ISCAS
Himadri Singh Raghav, Sachin Maheshwari, Mike Smart, Alexander Serb
2025 C conf
The Adiabatic Capacitive Neuron: A Cross CMOS Technology Performance Comparison.
ISCAS
Himadri Singh Raghav, Mike Smart, Sachin Maheshwari, Alexander Serb
2025 J jnl
Weight Mapping Properties of a Dual Tree Single Clock Adiabatic Capacitive Neuron.
CoRR
Mike Smart, Sachin Maheshwari, Himadri Singh Raghav, Alexander Serb
2023 — conf
A Memristor-based Tuneable Offset Comparator.
NEWCAS
Sachin Maheshwari, Jiaqi Wang, Alexander Serb, Themistoklis Prodromakis
2022 C conf
A CMOS-based Characterisation Platform for Emerging RRAM Technologies.
ISCAS
Andrea Mifsud, Jiawei Shen, Peilong Feng, Lijie Xie, Chaohan Wang, Yihan Pan, Sachin Maheshwari, Shady Agwa, Spyros Stathopoulos, Shiwei Wang, Alexander Serb, Christos Papavassiliou, Themis Prodromakis, Timothy G. Constandinou
2022 J jnl
A CMOS-based Characterisation Platform for Emerging RRAM Technologies.
CoRR
Andrea Mifsud, Jiawei Shen, Peilong Feng, Lijie Xie, Chaohan Wang, Yihan Pan, Sachin Maheshwari, Shady Agwa, Spyros Stathopoulos, Shiwei Wang, Alexander Serb, Christos Papavassiliou, Themis Prodromakis, Timothy G. Constandinou
2022 J jnl
An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sachin Maheshwari, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis
2022 J jnl
An Adiabatic Capacitive Artificial Neuron with RRAM-based Threshold Detection for Energy-Efficient Neuromorphic Computing.
CoRR
Sachin Maheshwari, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis
2021 J jnl
A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sachin Maheshwari, Viv A. Bartlett, Izzet Kale
2021 C conf
An Adiabatic Regenerative Capacitive Artificial Neuron.
ISCAS
Sachin Maheshwari, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis
2021 J jnl
Analysing and measuring the performance of memristive integrating amplifiers.
Int. J. Circuit Theory Appl.
Jiaqi Wang, Alexantrou Serb, Christos Papavassiliou, Sachin Maheshwari, Themis Prodromakis
2021 J jnl
Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sachin Maheshwari, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Andrea Mifsud, Lieuwe B. Leene, Jiawei Shen, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis
2021 J jnl
Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sachin Maheshwari, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Andrea Mifsud, Lieuwe B. Leene, Jiawei Shen, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis
2020 J jnl
Analysing and Measuring the Performance ofMemristive Integrating Amplifiers.
CoRR
Jiaqi Wang, Alexander Serb, Christos Papavassiliou, Sachin Maheshwari, Themistoklis Prodromakis
2020 J jnl
Hybrid CMOS/Memristor Circuit Design Methodology.
CoRR
Sachin Maheshwari, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Lieuwe B. Leene, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis
2020 J jnl
Optimal design of flux for submerged arc weld properties based on RSM coupled with GRA and PCA.
Int. J. Manuf. Technol. Manag.
Brijpal Singh, Zahid A. Khan, Arshad Noor Siddiquee, Sachin Maheshwari
2019 A conf
Adiabatic Implementation of Manchester Encoding for Passive NFC System.
DATE
Sachin Maheshwari, Izzet Kale
2019 — conf
Impact of Adiabatic Logic Families on the Power-Clock Generator Energy Efficiency.
PRIME
Sachin Maheshwari, Izzet Kale
2019 J jnl
Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach.
Integr.
Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale
2018 J jnl
Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication.
Integr.
Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale
2018 — conf
VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design.
PATMOS
Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale
2017 — conf
Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers.
ECCTD
Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale
2014 — conf
Logical effort based power-delay-product optimization.
ICACCI
Sachin Maheshwari, Jimit Patel, Sumit K. Nirmalkar, Anu Gupta
2013 — conf
Characterization of Logical Effort for Improved Delay.
VDAT
Sachin Maheshwari, Himadri Singh Raghav, Anu Gupta
2013 — conf
Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology.
VDAT
Sachin Maheshwari, Rameez Raza, Pramod Kumar, Anu Gupta
2013 — conf
Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology.
VDAT
Himadri Singh Raghav, Sachin Maheshwari, B. Prasad Singh
2011 — conf
Neural-Network- Based Modeling of Electric Discharge Machining Process.
SOCO
Pushpendrai Singh Bharti, Sachin Maheshwari, Chitra Sharma
2010 J jnl
Experimental results and analysis for Electrical Discharge Machining (EDM) of aluminium metal matrix composites with powder-mixed dielectric: Lenth's method.
Int. J. Manuf. Technol. Manag.
Shankar Singh, Sachin Maheshwari, Aloke Dey, Poorn Chandra Pandey
2007 J jnl
Optimisation of multiperformance characteristics in electric discharge machining of Aluminium Matrix Composites (AMCs) using Taguchi DOE methodology.
Int. J. Manuf. Res.
Shankar Singh, Sachin Maheshwari, Poorn Chandra Pandey