Sachin B. Patkar

67 papers A 1B 4C 5Misc 13Journal 27Unranked 17
YearRankTypeTitle / Venue / Authors
2024 Misc conf
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array.
VLSID
Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana
2024 C conf
In-Memory Mirroring: Cloning Without Reading.
VLSI-SoC
Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant
2024 J jnl
In-Memory Mirroring: Cloning Without Reading.
CoRR
Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant
2024 B conf
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory.
ASPDAC
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
2024 J jnl
Python-based DSL for generating Verilog model of Synchronous Digital Circuits.
CoRR
Mandar Datar, Dhruva S. Hegde, Vendra Durga Prasad, Manish Prajapati, Neralla Manikanta, Devansh Gupta, Janampalli Pavanija, Pratyush Pare, Akash, Shivam Gupta, Sachin B. Patkar
2024 — conf
Rapid Prototyping of CRYSTALS-Kyber Primitives on FPGA using Python-only HW-SW Flow.
VDAT
Dhruva S. Hegde, Mandar Datar, Manish Prajapati, Sachin B. Patkar, Gaurav Trivedi
2024 J jnl
Resistive Memory for Computing and Security: Algorithms, Architectures, and Platforms.
CoRR
Simranjeet Singh, Farhad Merchant, Sachin B. Patkar
2023 J jnl
CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism.
J. Syst. Archit.
Niraj N. Sharma, Riya Jain, Mohana Madhumita Pokkuluri, Sachin B. Patkar, Rainer Leupers, Rishiyur S. Nikhil, Farhad Merchant
2023 J jnl
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array.
CoRR
Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana
2023 — conf
Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies.
NANOARCH
Simranjeet Singh, Elmira Moussavi, Christopher Bengel, Sachin B. Patkar, Rainer Waser, Rainer Leupers, Vikas Rana, Vivek Pachauri, Stephan Menzel, Farhad Merchant
2023 — conf
Finite State Automata Design using 1T1R ReRAM Crossbar.
NEWCAS
Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant
2023 J jnl
Finite State Automata Design using 1T1R ReRAM Crossbar.
CoRR
Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant
2023 — conf
Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs.
ASP-DAC
Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant
2023 A conf
IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines.
ISLPED
Omar Ghazal, Simranjeet Singh, Tousif Rahman, Shengqi Yu, Yujin Zheng, Domenico Balsamo, Sachin B. Patkar, Farhad Merchant, Fei Xia, Alex Yakovlev, Rishad A. Shafik
2023 J jnl
IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines.
CoRR
Omar Ghazal, Simranjeet Singh, Tousif Rahman, Shengqi Yu, Yujin Zheng, Domenico Balsamo, Sachin B. Patkar, Farhad Merchant, Fei Xia, Alex Yakovlev, Rishad A. Shafik
2023 — conf
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar.
NEWCAS
Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Vikas Rana, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant
2023 J jnl
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar.
CoRR
Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Vikas Rana, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant
2023 J jnl
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory.
CoRR
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
2023 J jnl
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style.
CoRR
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
2023 J jnl
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style.
IEEE Embed. Syst. Lett.
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
2022 J jnl
Hardware Security Primitives using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs.
CoRR
Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant
2022 C conf
PA-PUF: A Novel Priority Arbiter PUF.
VLSI-SoC
Simranjeet Singh, Srinivasu Bodapati, Sachin B. Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant
2022 J jnl
PA-PUF: A Novel Priority Arbiter PUF.
CoRR
Simranjeet Singh, Srinivasu Bodapati, Sachin B. Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant
2020 — conf
Accelerated Stereo Vision Using Nvidia Jetson and Intel AVX.
CVIP (2)
Imran A. Syed, Mandar Datar, Sachin B. Patkar
2020 J jnl
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism.
CoRR
Riya Jain, Niraj N. Sharma, Farhad Merchant, Sachin B. Patkar, Rainer Leupers
2020 Misc conf
FPGA-Based Acceleration of LU decomposition for Analog and RF Circuit Simulation.
VLSID
Yogesh Mahajan, Shashank Obla, Mini K. Namboothiripad, Mandar J. Datar, Niraj N. Sharma, Sachin B. Patkar
2020 C conf
Real time System Implementation for Stereo 3D Mapping and Visual Odometry.
IPAS
Yashwant Temburu, Mandar Datar, Simranjeet Singh, Vaibhav Malviya, Sachin B. Patkar
2020 J jnl
Scalable implementation of particle filter-based visual object tracking on network-on-chip (NoC).
J. Real Time Image Process.
Pinalkumar Engineer, Rajbabu Velmurugan, Sachin B. Patkar
2020 J jnl
Single Storage Semi-Global Matching for Real Time Depth Processing.
CoRR
Prathmesh Sawant, Yashwant Temburu, Mandar Datar, Imran Ahmed, Vinayak Shriniwas, Sachin B. Patkar
2019 B conf
Computational Issues in Construction of 4-D Projective Spaces with Perfect Access Patterns for Higher Primes.
PaCT
Shreeniwas N. Sapre, Sachin B. Patkar, Supratim Biswas
2018 Misc conf
Lightweight Forth Programmable NoCs.
VLSID
Vinay B. Y. Kumar, Deval Shah, Mandar Datar, Sachin B. Patkar
2016 Misc conf
Relaxation Based Circuit Simulation Acceleration over CPU-FPGA.
VLSID
Vinay B. Y. Kumar, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, H. Narayanan, Sachin B. Patkar
2015 J jnl
Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies.
CoRR
Vinay B. Y. Kumar, Pinalkumar Engineer, Mandar Datar, Yatish Turakhia, Saurabh Agarwal, Sanket Diwale, Sachin B. Patkar
2015 — conf
Parallel two step random walk algorithm to analyze VLSI power grid networks.
VDAT
Satyabrata Dash, Vivek Bangera, Vinay B. Y. Kumar, Gaurav Trivedi, Sachin B. Patkar
2015 Misc conf
Parameterizable FPGA Framework for Particle Filter Based Object Tracking in Video.
VLSID
Pinalkumar Engineer, Rajbabu Velmurugan, Sachin B. Patkar
2014 — conf
FPGA-based implementation of M4RM for matrix multiplication over GF(2).
VDAT
Vivek Kumar, Vinay B. Y. Kumar, Sachin B. Patkar
2014 — conf
Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems.
VLSI-DAT
Janak Porwal, Sanket Diwale, Vinay B. Y. Kumar, Sachin B. Patkar
2014 C conf
Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping.
ICCD
Vinay B. Y. Kumar, Shovan Maity, Sachin B. Patkar
2013 — conf
Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields.
PECCS
Prateek Saxena, Vinay B. Y. Kumar, Dilawar Singh, H. Narayanan, Sachin B. Patkar
2013 Misc conf
Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy.
VLSI Design
Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar
2013 J jnl
Solution of PDEs-electrically coupled systems with electrical analogy.
Integr.
Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar
2012 — conf
FPGA Implementation of Particle Filter Based Object Tracking in Video.
ISED
Sumeet Agrawal, Pinal Engineer, Rajbabu Velmurugan, Sachin B. Patkar
2012 Misc conf
Two Graph Based Circuit Simulator for PDE-Electrical Analogy.
VLSI Design
Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar
2011 — conf
Double Precision Sparse Matrix Vector Multiplication Accelerator on FPGA.
PECCS
Sumedh Attarde, Siddharth Joshi, Yash Deshpande, Sunil Puranik, Sachin B. Patkar
2011 J jnl
Solution of Partial Differential Equations by electrical analogy.
J. Comput. Sci.
Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar
2010 J jnl
FPGA Based High Performance Double-Precision Matrix Multiplication.
Int. J. Parallel Program.
Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan
2010 — conf
Large Scale VLSI Circuit Simulation Using Point Relaxation.
CSC
Subhendu Roy, Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar
2009 C conf
A Pipelined Simulation Approach for Logic Emulation using Multi-FPGA Platforms.
ISCAS
Dinesh Baviskar, Sachin B. Patkar
2009 Misc conf
Acceleration of conjugate gradient method for circuit simulation using CUDA.
HiPC
Anirudh Maringanti, Viraj Athavale, Sachin B. Patkar
2009 Misc conf
Exploiting Hybrid Analysis in Solving Electrical Networks.
VLSI Design
V. Siva Sankar, H. Narayanan, Sachin B. Patkar
2009 Misc conf
FPGA Based High Performance Double-Precision Matrix Multiplication.
VLSI Design
Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan
2005 — conf
Algorithms For Scheduling Of Data Transfer Across FPGAs In A Grid.
ERSA
Janak Porwal, Sachin B. Patkar
2003 Misc conf
An Efficient Practical Heuristic For Good Ratio-Cut Partitioning.
VLSI Design
Sachin B. Patkar, H. Narayanan
2003 J jnl
Fast On-Line/Off-Line Algorithms for Optimal Reinforcement of a Network and its Connections with Principal Partition.
J. Comb. Optim.
Sachin B. Patkar, H. Narayanan
2003 J jnl
Improving graph partitions using submodular functions.
Discret. Appl. Math.
Sachin B. Patkar, H. Narayanan
2003 J jnl
The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function.
Discret. Appl. Math.
Madhav P. Desai, H. Narayanan, Sachin B. Patkar
2001 J jnl
A note on optimal covering augmentation for graphic polymatroids.
Inf. Process. Lett.
Sachin B. Patkar, H. Narayanan
2001 J jnl
Realization of set functions as cut functions of graphs and hypergraphs.
Discret. Math.
Satoru Fujishige, Sachin B. Patkar
2000 — conf
Fast On-Line/Off-Line Algorithms for Optimal Reinforcement of a Network and Its Connections with Principal Partition.
FSTTCS
Sachin B. Patkar, H. Narayanan
1999 Misc conf
Priority Scheduling in Parallel I/O Systems.
PDPTA
C. R. Venugopal, S. S. S. P. Rao, Sachin B. Patkar
1997 Misc conf
A New Partitioning Strategy Based on Supermodular Functions.
VLSI Design
Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan
1996 J jnl
Approximation Algorithms for Min-k-Overlap Problems Using the Principal Lattice of Partitions Approach.
J. Algorithms
H. Narayanan, Subir K. Roy, Sachin B. Patkar
1994 J jnl
Abstract and Generic Rigidity in the Plane.
J. Comb. Theory B
Sachin B. Patkar, Brigitte Servatius, K. V. Subrahmanyam
1994 B conf
Approximation Algorithms for Min-k-overlap Problems Using the Principal Lattice of Partitions Approach.
MFCS
H. Narayanan, Subir K. Roy, Sachin B. Patkar
1992 — conf
Fast Sequential and Randomised Parallel Algorithms for Rigidity and approximate Min k-cut.
FSTTCS
Sachin B. Patkar, H. Narayanan
1992 B conf
Principal Lattice of Partition of submodular functions on Graphs: Fast algorithms for Principal Partition and Generic Rigidity.
ISAAC
Sachin B. Patkar, H. Narayanan
1991 — conf
A Fast Algorithm for the Principle Partition of a Graph.
FSTTCS
Sachin B. Patkar, H. Narayanan