Sabyasachi Deyati

25 papers A 5C 1Misc 6Journal 5Unranked 7

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Efficient Parallel Testing and Implicit Cost-Driven Tuning of RF-MIMO Systems. IEEE Trans. Very Large Scale Integr. Syst. Suhasini Komarraju, Sabyasachi Deyati, Abhijit Chatterjee
2023	J	`jnl`	BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems. J. Electron. Test. Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee
2021	J	`jnl`	High Resolution Pulse Propagation Driven Trojan Detection in Digital Systems. J. Electron. Test. Sabyasachi Deyati, Barry J. Muldrey, Adit D. Singh, Abhijit Chatterjee
2020	J	`jnl`	Dynamic Test Stimulus Adaptation for Analog/RF Circuits Using Booleanized Models Extracted From Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sabyasachi Deyati, Barry J. Muldrey, Abhijit Chatterjee
2017	A	`conf`	BISCC: Efficient pre through post silicon validation of mixed-signal/RF systems using built in state consistency checking. DATE Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee
2017	A	`conf`	Concurrent built in test and tuning of beamforming MIMO systems using learning assisted performance optimization. ITC Sabyasachi Deyati, Barry J. Muldrey, Byunghoo Jung, Abhijit Chatterjee
2017	Misc	`conf`	Post-Silicon Validation: Automatic Characterization of RF Device Nonidealities via Iterative Learning Experiments on Hardware. VLSID Barry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee
2017	—	`—`	Scalable algorithms and design for debug hardware for test, validation and security of mixed signal/rf circuits and systems. Sabyasachi Deyati
2016	Misc	`conf`	Adaptive testing of analog/RF circuits using hardware extracted FSM models. VTS Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee
2016	—	`conf`	Concurrent Stimulus and Defect Magnitude Optimization for Detection of Weakest Shorts and Opens in Analog Circuits. ATS Barry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee
2016	A	`conf`	DE-LOC: Design validation and debugging under limited observation and control, pre- and post-silicon for mixed-signal systems. ITC Barry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee
2016	—	`conf`	Noise-Resilient SRAM Physically Unclonable Function Design for Security. ATS Sujay Pandey, Sabyasachi Deyati, Adit D. Singh, Abhijit Chatterjee
2016	Misc	`conf`	TRAP: Test Generation Driven Classification of Analog/RF ICs Using Adaptive Probabilistic Clustering Algorithm. VLSID Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee
2016	—	`conf`	Trojan detection in digital systems using current sensing of pulse propagation in logic gates. ISQED Sabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee
2015	—	`conf`	Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security. ATS Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee
2014	A	`conf`	A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time. ITC Bruce Querbach, Rahul Khanna, David Blankenbeckler, Yulan Zhang, Ronald T. Anderson, David G. Ellis, Zale T. Schoenborn, Sabyasachi Deyati, Patrick Chiang
2014	Misc	`conf`	Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuits. VTS Sabyasachi Deyati, Barry John Muldrey, Aritra Banerjee, Abhijit Chatterjee
2014	—	`conf`	High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure. ATS Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee
2014	J	`jnl`	Low Cost Signal Reconstruction Based Testing of RF Components using Incoherent Undersampling. J. Electron. Test. Debesh Bhatta, Aritra Banerjee, Sabyasachi Deyati, Nicholas Tzou, Abhijit Chatterjee
2013	—	`conf`	Low cost signal reconstruction based testing of RF components using incoherent undersampling. LATW Debesh Bhatta, Aritra Banerjee, Sabyasachi Deyati, Nicholas Tzou, Abhijit Chatterjee
2013	Misc	`conf`	RAVAGE: Post-silicon validation of mixed signal systems using genetic stimulus evolution and model tuning. VTS Barry John Muldrey, Sabyasachi Deyati, Michael Giardino, Abhijit Chatterjee
2013	Misc	`conf`	VAST: Post-Silicon VAlidation and Diagnosis of RF/Mixed-Signal Circuits Using Signature Tests. VLSI Design Sabyasachi Deyati, Aritra Banerjee, Barry John Muldrey, Abhijit Chatterjee
2012	C	`conf`	Pilot symbol driven monitoring of electrical degradation in RF transmitter systems using model anomaly diagnosis. IOLTS Sabyasachi Deyati, Aritra Banerjee, Abhijit Chatterjee
2012	A	`conf`	Validation signature testing: A methodology for post-silicon validation of analog/mixed-signal circuits. ICCAD Abhijit Chatterjee, Sabyasachi Deyati, Barry John Muldrey, Shyam Kumar Devarakond, Aritra Banerjee
2011	—	`conf`	An automated design methodology for yield aware analog circuit synthesis in submicron technology. ISQED Sabyasachi Deyati, Pradip Mandal