Saburo Muroga - RankMe

71 papers A* 3A 2C 1Misc 1Journal 34Unranked 5

Year	Rank	Type	Title / Venue / Authors
1999	—	`ch.`	Adders. The VLSI Handbook Naofumi Takagi, Haruyuki Tago, Charles R. Baugh, Saburo Muroga
1999	—	`ch.`	Basic Theory of Logic Functions. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Binary Decision Diagrams. The VLSI Handbook Shin-ichi Minato, Saburo Muroga
1999	—	`ch.`	CMOS. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Cell-Library Design Approach. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Dividers. The VLSI Handbook Naofumi Takagi, Saburo Muroga
1999	—	`ch.`	Emitter-Coupled Logic. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Expressions of Logic Functions. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Field-Programmable Gate Arrays. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Field-Programmable Gate Arrays. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Full-Custom and Semi-Custom Design. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Logic Properties of Transistor Circuits. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Logic Synthesis with AND and OR Gates in Multi-levels. The VLSI Handbook Yuichi Nakamura, Saburo Muroga
1999	—	`ch.`	Logic Synthesis with AND and OR Gates in Two Levels. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Logic Synthesis with NAND (or NOR) Gates in Multi-levels. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Logic Synthesis with a Minimum Number of Negative Gates. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Logic Synthesizer by the Transduction Method. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Logic Synthesizer with Optimizations in Two Phases. The VLSI Handbook Ko Yoshikawa, Saburo Muroga
1999	—	`ch.`	Mask-Programmable Gate Arrays. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Multipliers. The VLSI Handbook Naofumi Takagi, Charles R. Baugh, Saburo Muroga
1999	—	`ch.`	Pass Transistors. The VLSI Handbook Kazuo Yano, Saburo Muroga
1999	—	`ch.`	Programmable Logic Devices. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Sequential Networks with AND and OR Gates. The VLSI Handbook Saburo Muroga
1999	—	`ch.`	Simplification of Logic Expressions. The VLSI Handbook Saburo Muroga
1996	J	`jnl`	Design of logic circuits with wired-logic utilizing transduction method. Syst. Comput. Jpn. Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga
1996	J	`jnl`	Optimization methods for look-up table-type FPGAs based on permissible functions. Syst. Comput. Jpn. Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga
1995	—	`conf`	Optimization methods for lookup-table-based FPGAs using transduction method. ASP-DAC Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga
1993	Misc	`conf`	A Shared Memory Parallel Algorithm for Logic Synthesis. VLSI Design Chieng-Fai Lim, Prithviraj Banerjee, Kaushik De, Saburo Muroga
1991	A*	`conf`	A Resynthesis Approach for Network Optimization. DAC Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita
1991	J	`jnl`	Absolute Minimization of Completely Specified Switching Functions. IEEE Trans. Computers Sung Je Hong, Saburo Muroga
1991	J	`jnl`	Computer-Aided Logic Synthesis for VLSI Chips. Adv. Comput. Saburo Muroga
1991	A*	`conf`	Logic Optimization of MOS Networks. DAC Johnson Chan Limqueco, Saburo Muroga
1990	C	`conf`	SYLON-REDUCE: an MOS network optimization algorithms using permissible functions. ICCD Johnson Chan Limqueco, Saburo Muroga
1990	A*	`conf`	Timing Optimization for Multi-Level Combinational Networks. DAC Kuang-Chien Chen, Saburo Muroga
1989	A	`conf`	SYLON-DREAM: a multi-level network synthesizer. ICCAD Kuang-Chien Chen, Saburo Muroga
1989	J	`jnl`	The Transduction Method-Design of Logic Networks Based on Permissible Functions. IEEE Trans. Computers Saburo Muroga, Yahiko Kambayashi, Hung Chi Lai, Jay Niel Culliney
1988	J	`jnl`	Design of MOS networks in single-rail input logic for incompletely specified functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hung Chi Lai, Saburo Muroga
1988	A	`conf`	Input assignment algorithm for decoded-PLAs with multi-input decoders. ICCAD Kuang-Chien Chen, Saburo Muroga
1987	J	`jnl`	Derivation of Minimal Sums for Completely Specified Functions. IEEE Trans. Computers Robert Brian Cutler, Saburo Muroga
1987	J	`jnl`	Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of IEEE Trans. Computers Hung Chi Lai, Saburo Muroga
1986	J	`jnl`	Properties of Wired Logic. IEEE Trans. Computers Yahiko Kambayashi, Saburo Muroga
1985	J	`jnl`	Minimal covering problem and PLA minimization. Int. J. Parallel Program. Ming Huei Young, Saburo Muroga
1985	J	`jnl`	Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables. IEEE Trans. Computers Ming Huei Young, Saburo Muroga
1984	J	`jnl`	Parallel multipliers with NOR gates based on G-minimum adders. Int. J. Parallel Program. Ging-Shung Yu, Saburo Muroga
1983	J	`jnl`	Parallel Binary Adders with a Minimum Number of Connections. IEEE Trans. Computers Akito Sakurai, Saburo Muroga
1982	J	`jnl`	Logic Networks of Carry-Save Adders. IEEE Trans. Computers Hung Chi Lai, Saburo Muroga
1980	J	`jnl`	Useless prime implicants of incompletely specified multiple-output switching functions. Int. J. Parallel Program. Robert Brian Cutler, Saburo Muroga
1979	J	`jnl`	Comments on "Computing Irredundant Normal Forms from Abbreviated Presence Functions". IEEE Trans. Computers Robert Brian Cutler, Saburo Muroga
1979	J	`jnl`	Comments on "Generalization of Consensus Theory and Application to the Minimization of Boolean Functions". IEEE Trans. Computers Robert Brian Cutler, Saburo Muroga
1979	J	`jnl`	Minimum Parallel Binary Adders with NOR (NAND) Gates. IEEE Trans. Computers Hung Chi Lai, Saburo Muroga
1979	J	`jnl`	Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions. IEEE Trans. Computers Jay Niel Culliney, Ming Huei Young, Tomoyasu Nakagawa, Saburo Muroga
1976	J	`jnl`	Minimization of Logic Networks Under a Generalized Cost Function. IEEE Trans. Computers Saburo Muroga, Hung Chi Lai
1974	J	`jnl`	Optimal One-Bit Full Adders With Different Types of Gates. IEEE Trans. Computers Tso-Kai Liu, Keith R. Hohulin, Lih-Er Shiau, Saburo Muroga
1974	J	`jnl`	Redundancy check technique for designing optimal networks by branch-and-bound method. Int. J. Parallel Program. Hung Chi Lai, Tomoyasu Nakagawa, Saburo Muroga
1972	J	`jnl`	An implicit enumeration program for zero-one integer programming. Int. J. Parallel Program. Toshihide Ibaraki, Tso-Kai Liu, Charles R. Baugh, Saburo Muroga
1972	J	`jnl`	Design of Optimal Switching Networks by Integer Programming. IEEE Trans. Computers Saburo Muroga, Toshihide Ibaraki
1972	J	`jnl`	Optimal Networks of NOR-OR Gates for Functions of Three Variables. IEEE Trans. Computers Charles R. Baugh, C. S. Chandersekaran, Richard S. Swee, Saburo Muroga
1971	J	`jnl`	Synthesis of Networks with a Minimum Number of Negative Gates. IEEE Trans. Computers Toshihide Ibaraki, Saburo Muroga
1971	J	`jnl`	Technical Note - Results in Using Gomory's All-Integer Integer Algorithm to Design Optimum Logic Networks. Oper. Res. Charles R. Baugh, Toshihide Ibaraki, Saburo Muroga
1971	—	`book`	Threshold logic and its applications. Saburo Muroga
1970	J	`jnl`	Adaptive Linear Classifier by Linear Programming. IEEE Trans. Syst. Sci. Cybern. Toshihide Ibaraki, Saburo Muroga
1970	J	`jnl`	Enumeration of Threshold Functions of Eight Variables. IEEE Trans. Computers Saburo Muroga, Teiichi Tsuboi, Charles R. Baugh
1966	J	`jnl`	Lower Bound of the Number of Threshold Functions. IEEE Trans. Electron. Comput. Saburo Muroga, Iwao Toda
1965	J	`jnl`	Generation and Asymmetry of Self-Dual Threshold Functions. IEEE Trans. Electron. Comput. Saburo Muroga
1965	J	`jnl`	Lower Bounds of the Number of Threshold Functions and a Maximum Weight. IEEE Trans. Electron. Comput. Saburo Muroga
1962	—	`conf`	Generation of self-dual threshold functions and lower bounds of the number of threshold functions and a maximum weight SWCT Saburo Muroga
1961	—	`conf`	Functional forms of majority functions and a necessary and sufficient condition for their realizability SWCT Saburo Muroga
1961	—	`conf`	Two problems on threshold functions SWCT Calvin C. Elgot, Saburo Muroga
1959	J	`jnl`	The Parametron Digital Computer MUSASINO-1. IRE Trans. Electron. Comput. Saburo Muroga, Kensuke Takashima
1959	—	`conf`	The principle of majority decision logical elements and the complexity of their circuits. IFIP Congress Saburo Muroga
1957	J	`jnl`	On the capacity of a noisy continuous channel. IRE Trans. Inf. Theory Saburo Muroga