S. Srinivasan

21 papers A 1C 3Misc 4Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2011 — conf
Towards Quick Solutions for Generalized Placement Problem.
ISED
S. Srinivasan, V. Kamakoti, A. Bhattacharya
2010 J jnl
Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation.
IEEE Trans. Broadcast.
Kavish Seth, V. Kamakoti, S. Srinivasan
2007 — conf
Rapid Abstract Control Model for Signal Processing Implementation.
SiPS
Kannan Gaddam, Nitin Chandrachoodan, S. Srinivasan
2006 J jnl
A parallel algorithm, architecture and FPGA realization for landmark determination and map construction in a planar unknown environment.
Parallel Comput.
P. Rajesh Kumar, K. Sridharan, S. Srinivasan
2006 Misc conf
Ultra Folded High-Speed Architectures for Reed-Solomon Decoders.
VLSI Design
Kavish Seth, K. N. Viswajith, S. Srinivasan, V. Kamakoti
2005 J jnl
Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization.
J. Syst. Archit.
Seetharaman Ramachandran, S. Srinivasan
2004 Misc conf
A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation.
VLSI Design
Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar
2003 — conf
A Distributed Memory Architecture for Morphological Image Processing.
ITCC
A. Durga Kishore, S. Srinivasan
2003 Misc conf
A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI.
VLSI Design
Srikar Movva, S. Srinivasan
2003 C conf
Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization.
DSD
Seetharaman Ramachandran, S. Srinivasan
2003 — conf
Reduced Memory Implementation of Modified Serial Watershed Algorithm Based On Ordered Queue.
ITCC
Kumud Prakash Gupta, S. Srinivasan
2002 J jnl
A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse-grain Parallelism.
VLSI Design
Seetharaman Ramachandran, S. Srinivasan
2002 J jnl
A Novel, Automatic Quality Control Scheme for Real Time Image Transmission.
VLSI Design
Seetharaman Ramachandran, S. Srinivasan
2002 J jnl
A fast, FPGA-based MPEG-2 video encoder with a novel automatic quality control scheme.
Microprocess. Microsystems
Seetharaman Ramachandran, S. Srinivasan
2002 — conf
VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme.
ASP-DAC/VLSI Design
Kavish Seth, S. Srinivasan
2001 A conf
FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression.
FPGA
Seetharaman Ramachandran, S. Srinivasan
2000 C conf
A programmable pruning level control based MPEG video encoder.
ISCAS
Seetharaman Ramachandran, S. Srinivasan
2000 C conf
Design and implementation of an EPLD-based variable length coder for real time image compression applications.
ISCAS
Seetharaman Ramachandran, S. Srinivasan
1999 — conf
EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression.
ISCAS (3)
Seetharaman Ramachandran, S. Srinivasan, R. Chen
1999 Misc conf
Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs.
VLSI Design
D. V. R. Murthy, Seetharaman Ramachandran, S. Srinivasan
1986 J jnl
New design for an 82720-based colour graphics generator.
Microprocess. Microsystems
P. Prabhakar Rao, S. Srinivasan