S. P. Joy Vasantha Rani

14 papers Journal 12Unranked 2

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Analysis of FPGA Architecture with Hybrid Logic Blocks Based on ULG and LUT. J. Circuits Syst. Comput. P. Sudhanya, S. P. Joy Vasantha Rani
2022	J	`jnl`	Approximate Multipliers Design Using Approximate Adders for Image Processing Applications. J. Circuits Syst. Comput. S. P. Joy Vasantha Rani, J. R. Lourdu Jennifer, P. Sudhanya
2022	J	`jnl`	Realization of Deep Learning Based Embedded Soft Sensor for Bioprocess Application. Intell. Autom. Soft Comput. V. V. S. Vijaya Krishna, N. Pappa, S. P. Joy Vasantha Rani
2021	J	`jnl`	Wire-Length and Run-Time Optimization in FPGA Placement Using Hybrid Iterative Algorithms. J. Circuits Syst. Comput. P. Sudhanya, S. P. Joy Vasantha Rani
2020	J	`jnl`	A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR Filter Implementation Using Hardware-Software Co-Design. J. Circuits Syst. Comput. Chandran Ranjith, S. P. Joy Vasantha Rani
2020	J	`jnl`	Nonlinear Controller: Voltage Controlled PFC-Based Fuzzy MDPSM Controller with Predictive Input Voltage. J. Circuits Syst. Comput. R. Thangam, S. P. Joy Vasantha Rani
2020	J	`jnl`	Performance analysis of intrinsic embedded evolvable hardware using memetic and genetic algorithms. Int. J. Bio Inspired Comput. Ranjith Chandrasekharan, S. P. Joy Vasantha Rani
2019	J	`jnl`	Automatic fault isolation and restoration of distribution system using JADE based Multi-Agents. Turkish J. Electr. Eng. Comput. Sci. Indhumathi Chellaswamy, S. P. Joy Vasantha Rani
2019	J	`jnl`	Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation. J. Circuits Syst. Comput. Senthil Sivakumar, S. P. Joy Vasantha Rani
2018	J	`jnl`	An ADC BIST using on-chip ramp generation and digital ORA. Microelectron. J. Senthil Sivakumar, S. P. Joy Vasantha Rani
2015	J	`jnl`	Pipelined hardware design of self tuning controller with on-chip parameter estimator. Int. J. High Perform. Syst. Archit. S. P. Joy Vasantha Rani
2012	—	`conf`	Reconfigurable RNS FIR Filter Using Higher Radix Multiplier. ACITY (3) J. Britto Pari, S. P. Joy Vasantha Rani
2009	J	`jnl`	Field Programmable Gate Array based floating point hardware design of recursive k-means clustering algorithm for Radial Basis Function Neural Network. Int. J. Intell. Syst. Technol. Appl. S. P. Joy Vasantha Rani, P. Kanagasabapathy, L. Suganthi
2004	—	`conf`	Design of Neural Network on FPGA. ESA/VLSI S. P. Joy Vasantha Rani, P. Kanagasabapathy