S. Kala

20 papers C 2Misc 2Journal 5Unranked 11
YearRankTypeTitle / Venue / Authors
2025 J jnl
MdCSR: A Memory-Efficient Sparse Matrix Compression Format.
IEEE Embed. Syst. Lett.
Noble G, Nalesh S, S. Kala, Salim Ullah, Akash Kumar
2024 C conf
A Novel CNN Architecture for Herb Classification.
TENCON
Sweety Kunjachan, Anjuru Muni Santhosh, S. Kala
2024 — conf
FPGA-Based Acceleration of Homomorphic Convolution with Plaintext Kernels - Extended Abstract.
SPACE
Rohith George Ninan, S. Kala
2023 J jnl
A physically unclonable function architecture with multiple responses on FPGA.
Int. J. Embed. Syst.
M. A. Muneeb, Nalesh S, S. Kala
2023 — conf
Approximate CNN on FPGA Using Toom-Cook Multiplier.
iSES
Abhinav Kalvacherla, Rachana George, Nalesh S, S. Kala
2023 — conf
Bit-Flip Attack Detection for Secure Sparse Matrix Computations on FPGA.
APCCAS
Noble G, Nalesh S, S. Kala
2023 Misc conf
MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles.
VLSID
Noble G, Nalesh S, S. Kala
2022 — conf
Adiabatic Physical Unclonable Function Using Cross-Coupled Pair.
iSES
Vishnu Bajjuri, Nalesh S, Sree Ranjani Rajendran, S. Kala
2021 — conf
Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA.
SoCC
Mahesh M, Nalesh S, S. Kala
2021 — conf
Hardware Acceleration of SpMV Multiplier for Deep Learning.
VDAT
Mahesh Mahadurkar, Nalesh Sivanandan, S. Kala
2019 — conf
Efficient Hardware Acceleration of Convolutional Neural Networks.
SoCC
S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan
2019 J jnl
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture.
IEEE Trans. Very Large Scale Integr. Syst.
S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan
2019 J jnl
Radix-4
IET Comput. Digit. Tech.
S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan
2019 Misc conf
UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs.
VLSID
S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan
2018 — conf
A Hardware Accelerator for Convolutional Neural Network Using Fast Fourier Transform.
VDAT
S. Kala, Babita R. Jose, Debdeep Paul, Jimson Mathew
2018 — conf
Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA.
ISED
S. Kala, Debdeep Paul, Babita R. Jose, Nalesh Sivanandan
2018 — conf
Two dimensional FFT architecture based on radix-4
DTIS
S. Kala, Nalesh Sivanandan, Babita R. Jose, Jimson Mathew, Marco Ottavi
2015 J jnl
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture.
J. Low Power Electron.
S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2014 — conf
Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems.
ISED
S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2013 C conf
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit.
ISCAS
S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan