S. K. Nandy - RankMe

143 papers A* 6A 3B 3C 8Misc 25Journal 35Unranked 61

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Symmetric Convolutional Filters: A Novel Way to Constrain Parameters in CNN. CoRR Harish Agrawal, Sumana T., S. K. Nandy
2021	J	`jnl`	Factorization of Boolean Polynomials: Parallel Algorithms and Experimental Evaluation. Program. Comput. Softw. Pavel G. Emelyanov, Madhava Krishna, Vadiraj Kulkarni, S. K. Nandy, Denis K. Ponomaryov, Soumyendu Raha
2020	J	`jnl`	Towards Accelerated Genome Informatics on Parallel HPC Platforms: The ReneGENE-GI Perspective. J. Signal Process. Syst. Santhi Natarajan, N. Krishna Kumar, Debnath Pal, S. K. Nandy
2019	Misc	`conf`	A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. VLSID Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
2019	Misc	`conf`	Applying Modified Householder Transform to Kalman Filter. VLSID Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
2019	J	`jnl`	EX-DRIVE: An Execution Driven Functional Verification Flow. J. Low Power Electron. Ipsita Biswas Mahapatra, S. K. Nandy
2019	—	`conf`	Parallel Factorization of Boolean Polynomials. Ershov Informatics Conference Vadiraj Kulkarni, Pavel G. Emelyanov, Denis K. Ponomaryov, Madhava Krishna, Soumyendu Raha, S. K. Nandy
2018	J	`jnl`	A Hardware Architecture for Radial Basis Function Neural Network Classifier. IEEE Trans. Parallel Distributed Syst. Mahnaz Mohammadi, Akhil Krishna, Nalesh Sivanandan, S. K. Nandy
2018	—	`conf`	Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design. ARC Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2018	J	`jnl`	Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design. CoRR Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2018	—	`conf`	An Algorithm - Architecture Co-Designed System for Dynamic Execution-Driven Pre-Silicon Verification. ISED Ipsita Biswas Mahapatra, S. K. Nandy
2018	Misc	`conf`	Design Space Exploration of an Execution-Driven Functional Simulation Methodology. VLSID Ipsita Biswas Mahapatra, Utkarsh Agarwal, Chandrashekhar Azad, S. K. Nandy
2018	J	`jnl`	Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
2018	J	`jnl`	Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization. IEEE Trans. Parallel Distributed Syst. Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2018	—	`conf`	ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs. ARC Santhi Natarajan, N. Krishna Kumar, Debnath Pal, S. K. Nandy
2018	—	`conf`	ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short Reads. ARC Santhi Natarajan, N. Krishna Kumar, H. V. Anuchan, Debnath Pal, S. K. Nandy
2017	—	`ed.`	2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2017, Pythagorion, Greece, July 17-20, 2017 SAMOS Yale N. Patt, S. K. Nandy
2017	J	`jnl`	Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. Parallel Process. Lett. Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2017	J	`jnl`	Energy aware synthesis of application kernels through composition of data-paths on a CGRA. Integr. Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan
2017	Misc	`conf`	REDEFINE CASES Kavitha T. Madhu, Tarun Singla, S. K. Nandy, Ranjani Narayan, François Neumann, Philippe Baufreton
2016	J	`jnl`	Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. CoRR Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2016	J	`jnl`	Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design. CoRR Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2016	—	`conf`	AccuRA: Accurate alignment of short reads on scalable reconfigurable accelerators. SAMOS Santhi Natarajan, N. Krishna Kumar, Debnath Pal, S. K. Nandy
2016	Misc	`conf`	Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation. VLSID Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2016	J	`jnl`	Efficient Realization of Householder Transform through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2016	Misc	`conf`	Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic. VLSID Farhad Merchant, Nimash Choudhary, S. K. Nandy, Ranjani Narayan
2016	—	`conf`	Flexible resource allocation and management for application graphs on ReNÉ MPSoC. PARMA-DITAM@HiPEAC Kavitha T. Madhu, Anuj Rao, Saptarsi Das, Madhava Krishna C., S. K. Nandy, Ranjani Narayan
2016	—	`conf`	Performance Evaluation of Feed-Forward Backpropagation Neural Network for Classification on a Reconfigurable Hardware Architecture. ARC Mahnaz Mohammadi, Rohit Ronge, Sanjay Sri Vallabh Singapuram, S. K. Nandy
2016	J	`jnl`	REFRESH: REDEFINE for Face Recognition Using SURE Homogeneous Cores. IEEE Trans. Parallel Distributed Syst. Gopinath Mahale, Hamsika Mahale, S. K. Nandy, Ranjani Narayan
2016	J	`jnl`	Role based shared memory access control mechanisms in NoC based MP-SoC. Nano Commun. Networks Arnab Kumar Biswas, S. K. Nandy
2016	Misc	`conf`	VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks. VLSID Gopinath Mahale, Soumitra Kumar Nandy, Eshan Bhatia, S. K. Nandy, Ranjani Narayan
2015	Misc	`conf`	A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks. VLSID Mahnaz Mohammadi, Nitin Satpute, Rohit Ronge, Jayesh R. Chandiramani, S. K. Nandy, Aamir Raihan, Tanmay Verma, Ranjani Narayan, Sukumar Bhattacharya
2015	—	`conf`	A deterministic, minimal routing algorithm for a toroidal, rectangular honeycomb topology using a 2-tupled relative address. SoCC Alexander Fell, S. K. Nandy, Ranjani Narayan
2015	—	`conf`	Compiling HPC Kernels for the REDEFINE CGRA. HPCC/CSS/ICESS Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2015	—	`conf`	Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array. iNIS Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan
2015	Misc	`conf`	Hardware Solution for Real-Time Face Recognition. VLSID Gopinath Mahale, Hamsika Mahale, Arnav Goel, S. K. Nandy, S. Bhattacharya, Ranjani Narayan
2015	—	`conf`	High Performance Computing Cloud - A Platform-as-a-Service Perspective. CCBD Pratima Ashok Dhuldhule, J. Lakshmi, S. K. Nandy
2015	B	`conf`	Location Obfuscation for Location Data Privacy. SERVICES Vaibhav Ankush Kachore, J. Lakshmi, S. K. Nandy
2015	Misc	`conf`	Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. VLSID Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2015	J	`jnl`	Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat. Circuits Syst. Signal Process. Arnab Kumar Biswas, S. K. Nandy, Ranjani Narayan
2015	J	`jnl`	Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture. J. Low Power Electron. S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2014	J	`jnl`	A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. J. Syst. Archit. Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant, Santhi Natarajan, Ipsita Biswas, Adithya Pulli, S. K. Nandy, Ranjani Narayan
2014	—	`conf`	Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs. ICSAMOS Mahesh Mahadurkar, Farhad Merchant, Arka Maity, Kapil Vatwani, Ishan Munje, Nandhini Gopalan, S. K. Nandy, Ranjani Narayan
2014	Misc	`conf`	Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR). VLSID Farhad Merchant, Anupam Chattopadhyay, Ganesh Garga, S. K. Nandy, Ranjani Narayan, Nandhini Gopalan
2014	—	`conf`	Efficient Storage of Big-Data for Real-Time GPS Applications. BDCloud Pavan Kumar Akulakrishna, J. Lakshmi, S. K. Nandy
2014	—	`conf`	Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation. ASAP Zoltán Endre Rákossy, Farhad Merchant, Axel Acosta-Aponte, S. K. Nandy, Anupam Chattopadhyay
2014	—	`conf`	Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems. ISED S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2014	—	`conf`	Hardware architecture of bi-cubic convolution interpolation for real-time image scaling. FPT Gopinath Mahale, Hamsika Mahale, Rajesh Babu Parimi, S. K. Nandy, S. Bhattacharya
2014	—	`conf`	Real Time Routing in Road Networks. BDCloud Aakriti Gupta, J. Lakshmi, S. K. Nandy
2014	C	`conf`	Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation. VLSI-SoC Zoltán Endre Rákossy, Farhad Merchant, Axel Acosta-Aponte, S. K. Nandy, Anupam Chattopadhyay
2014	—	`conf`	Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath. ICSAMOS Kavitha T. Madhu, Saptarsi Das, Madhava Krishna C., Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2013	—	`conf`	Elastic Resources Framework in IaaS, Preserving Performance SLAs. IEEE CLOUD Mohit Dhingra, J. Lakshmi, S. K. Nandy, Chiranjib Bhattacharyya, Kanchi Gopinath
2013	C	`conf`	High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. ISCAS S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan
2013	Misc	`conf`	Optimal Pipeline Depth and Supply Voltage for Power-constrained Processors. VLSI Design Abhijit Giri, S. K. Nandy
2013	—	`conf`	Virtual Machine Placement Optimization Supporting Performance SLAs. CloudCom (1) Ankit Anand, J. Lakshmi, S. K. Nandy
2012	—	`conf`	Resource Usage Monitoring in Clouds. GRID Mohit Dhingra, J. Lakshmi, S. K. Nandy
2011	—	`conf`	A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support. ISED Alok Baluni, Farhad Merchant, S. K. Nandy, Srinivasan Balakrishnan
2011	C	`conf`	A Method for Flexible Reduction over Binary Fields using a Field Multiplier. SECRYPT Saptarsi Das, Keshavan Varadarajan, Ganesh Garga, Rajdeep Mondal, Ranjani Narayan, S. K. Nandy
2011	—	`conf`	Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. ARC Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan
2011	—	`conf`	Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture. FPT Ratna Krishnamoorthy, Masahiro Fujita, Keshavan Varadarajan, S. K. Nandy
2011	—	`conf`	USHA: Unified software and hardware architecture for video decoding. SASP Adarsha Rao, S. K. Nandy, Hristo Nikolov, Ed F. Deprettere
2010	—	`conf`	Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. ISVLSI Prasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2010	—	`conf`	Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. ICSAMOS Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2010	—	`conf`	Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture. ICSAMOS N. Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2010	C	`conf`	I/O Virtualization Architecture for Security. CIT J. Lakshmi, S. K. Nandy
2010	Misc	`conf`	Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. CASES Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita
2009	—	`conf`	An Input Triggered Polymorphic ASIC for H.264 Decoding. ASAP Adarsha Rao, Mythri Alle, Sainath V, Reyaz Shaik, Rajashekhar Chowhan, Sreeramula Sankaraiah, Sravanthi Mantha, S. K. Nandy, Ranjani Narayan
2009	—	`conf`	Architecture of Run-Time Reconfigurable Channel Decoder. ICC Ritesh Rajore, S. K. Nandy, H. S. Jamadagni
2009	—	`conf`	Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. ARC Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan
2009	—	`conf`	Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT. SoCC Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan
2009	—	`conf`	High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures. ICSAMOS Ganesh Garga, David Guevorkian, S. K. Nandy, H. S. Jamadagni
2009	—	`conf`	I/O Device Virtualization in the Multi-core era, a QoS Perspective. GPC Workshops J. Lakshmi, S. K. Nandy
2009	J	`jnl`	REDEFINE: Runtime reconfigurable polymorphic ASIC. ACM Trans. Embed. Comput. Syst. Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan
2009	—	`conf`	RETHROTTLE: Execution throttling in the REDEFINE SoC architecture. ICSAMOS A. N. Satrawala, S. K. Nandy
2009	Misc	`conf`	Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. CASES Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan
2008	—	`conf`	Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. ASAP Adarsha Rao, Mythri Alle, S. K. Nandy, Ranjani Narayan
2008	J	`jnl`	On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation. J. Syst. Archit. Subhasis Banerjee, G. Surendra, S. K. Nandy
2008	—	`conf`	RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. ASAP Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan
2008	—	`conf`	Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network. SoC Ganesh Garga, Mythri Alle, Keshavan Varadarajan, S. K. Nandy, H. S. Jamadagni
2008	—	`conf`	Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. ASAP Ritesh Rajore, Ganesh Garga, H. S. Jamadagni, S. K. Nandy
2008	—	`conf`	Synthesis of application accelerators on Runtime Reconfigurable Hardware. ASAP Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan
2007	J	`jnl`	Low-Power Hierarchical Scan Test for Multiple Clock Domains. J. Low Power Electron. Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy
2007	—	`conf`	Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. ASP-DAC Subhasis Banerjee, G. Surendra, S. K. Nandy
2007	B	`conf`	REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. FPL A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2006	—	`conf`	A Cost Effective Pipelined Divider for Double Precision Floating Point Number. ASAP Sandeep B. Singh, Jayanta Biswas, S. K. Nandy
2006	—	`conf`	A Framework for Measurement of End-To-End Qos Requirements in Loosely Coupled Systems. AINA (2) K. Kalapriya, S. K. Nandy, Nanjangud C. Narendra
2006	C	`conf`	Framework for Enabling Highly Available Distributed Applications for Utility Computing. ISPA J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan
2006	—	`conf`	High Performance VLSI Architecture Design for H.264 CAVLC Decoder. ASAP Mythri Alle, Jayanta Biswas, S. K. Nandy
2006	J	`jnl`	Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations. J. Embed. Comput. G. Surendra, Subhasis Banerjee, S. K. Nandy
2006	A*	`conf`	Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. MICRO Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Bharadwaj Amrutur, Ravi R. Iyer, Srihari Makineni, Donald Newell
2006	—	`conf`	On the Implementation of a Streaming Video over Peer to Peer network using Middleware Components. ICN/ICONS/MCL K. Kalapriya, S. K. Nandy
2006	—	`conf`	Towards Self-Composing, Prioritized and Consequential Services. IEEE SCC Raghu Anantharangachar, Gorur N. Shrinivas, S. K. Nandy
2005	—	`conf`	A Framework for QoS Adaptive Grid Meta Scheduling. DEXA Workshops K. C. Nainwal, J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan
2005	—	`conf`	Functional and architectural adaptation in pervasive computing environments. MPAC Nanjangud C. Narendra, Umesh Bellur, S. K. Nandy, K. Kalapriya
2005	B	`conf`	Throughput Driven, Highly Available Streaming Stored Playback Video Service over a Peer-to-Peer Network. AINA K. Kalapriya, S. K. Nandy
2004	—	`conf`	A framework for resource discovery in pervasive computing for mobile aware task execution. Conf. Computing Frontiers K. Kalapriya, S. K. Nandy, Deepti Srinivasan, R. Uma Maheshwari, V. Satish
2004	—	`conf`	An Architectural View of the Entities Required for Execution of Task in Pervasive Space. FTDCS K. Kalapriya, S. K. Nandy, V. Satish, R. Uma Maheshwari, Deepti Srinivas
2004	—	`conf`	Can Streaming Of Stored Playback Video Be Supported On Peer to Peer Infrastructure? AINA (2) K. Kalapriya, S. K. Nandy, K. Venkatesh Babu
2004	—	`conf`	Exploiting program execution phases to trade power and performance for media workload. ASP-DAC Subhasis Banerjee, G. Surendra, S. K. Nandy
2004	J	`jnl`	On the Correctness of Program Execution When Cache Coherence Is Maintained Locally at Data-Sharing Boundaries in Distributed Shared Memory Multiprocessors. Int. J. Parallel Program. H. Sarojadevi, S. K. Nandy, Srinivasan Balakrishnan
2004	—	`conf`	On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort. WMPI G. Surendra, Subhasis Banerjee, S. K. Nandy
2004	—	`conf`	Power-performance trade-off using pipeline delays. ASP-DAC G. Surendra, Subhasis Banerjee, S. K. Nandy
2003	A*	`conf`	A complexity effective communication model for behavioral modeling of signal processing applications. DAC M. N. V. Satya Kiran, M. N. Jayram, Pradeep Rao, S. K. Nandy
2003	—	`ch.`	Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. Embedded Software for SoC G. Surendra, Subhasis Banerjee, S. K. Nandy
2003	A	`conf`	Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. DATE G. Surendra, Subhasis Banerjee, S. K. Nandy
2003	A	`conf`	Multivoltage scheduling with voltage-partitioned variable storage. ISLPED Amitabh Menon, S. K. Nandy, Mahesh Mehendale
2003	J	`jnl`	On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications. Int. J. Parallel Program. G. Surendra, Subhasis Banerjee, S. K. Nandy
2003	—	`conf`	Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures. Asia-Pacific Computer Systems Architecture Conference Pradeep Rao, S. K. Nandy, M. N. V. Satya Kiran
2003	—	`conf`	Traffic Profiling for Efficient Network Resource Utilization. International Conference on Internet Computing K. Kalapriya, B. R. Raghucharan, Abhijit M. Lele, S. K. Nandy
2002	—	`conf`	Enforcing Cache Coherence at Data Sharing Boundaries without Global Control: A Hardware-Software Approach (Research Note). Euro-Par H. Sarojadevi, S. K. Nandy, Srinivasan Balakrishnan
2002	—	`conf`	Multithreaded Architectural Support for Speculative Trace Scheduling in VLIW Processors. SBCCI Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, S. Balakrishanan
2002	Misc	`conf`	On the Benefits of Speculative Trace Scheduling in VLIW Processors. PDPTA Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, Srinivasan Balakrishnan
2002	C	`conf`	Speculative Trace Scheduling in VLIW Processors. ICCD Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, Srinivasan Balakrishnan
2001	Misc	`conf`	Architecture of Reconfigurable a Low Power Gigabit AT Switch. VLSI Design Abhijit M. Lele, S. K. Nandy
2001	—	`conf`	Content adaptive motion estimation for mobile video encoders. ISCAS (2) Arshad Ahmed, S. K. Nandy, Paul Sathya
2001	Misc	`conf`	ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. VLSI Design G. Surendra, S. K. Nandy, Paul Sathya
2000	A	`conf`	Design Space Exploration for Orividing QoS Within the Harmony Framework. IEEE International Conference on Multimedia and Expo (I) Abhijit M. Lele, S. K. Nandy, Dick H. J. Epema
2000	J	`jnl`	Harmony - An Architecture for Providing Quality of Service in Mobile Computing Environments. J. Interconnect. Networks Abhijit M. Lele, S. K. Nandy, Dick H. J. Epema
2000	A*	`conf`	Power minimization using control generated clocks. DAC M. Srikanth Rao, S. K. Nandy
2000	J	`jnl`	Reconfigurable Filter Coprocessor Architecture for DSP Applications. J. VLSI Signal Process. S. Ramanathan, S. K. Nandy, V. Visvanathan
1999	J	`jnl`	A computational engine for multirate FIR digital filtering. Signal Process. S. Ramanathan, V. Visvanathan, S. K. Nandy
1999	J	`jnl`	Architectural Synthesis of Computational Engines for Subband Adaptive Filtering. J. VLSI Signal Process. S. Ramanathan, V. Visvanathan, S. K. Nandy
1999	C	`conf`	Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. ICCD Avinash K. Gautam, V. Visvanathan, S. K. Nandy
1999	Misc	`conf`	Harmony - A Framework for Providing Quality of Service in Wireless Mobile Computing Environment. HiPC Abhijit M. Lele, S. K. Nandy
1999	J	`jnl`	Synthesis of ASIPs for DSP algorithms. Integr. S. Ramanathan, V. Visvanathan, S. K. Nandy
1999	Misc	`conf`	Synthesis of Configurable Architectures for DSP Algorithms. VLSI Design S. Ramanathan, V. Visvanathan, S. K. Nandy
1997	Misc	`conf`	Modeling multi-threaded architectures in PAMELA for real-time high performance applications. HiPC Srinivasan Balakrishnan, S. K. Nandy, Arjan J. C. van Gemund
1997	J	`jnl`	Signal compression through spatial frequency-based motion estimation. Integr. Vinod Menezes, S. K. Nandy, Biswadip Mitra
1995	J	`jnl`	Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. IEEE Trans. Very Large Scale Integr. Syst. Debabrata Ghosh, S. K. Nandy
1994	Misc	`conf`	A 600MHz Half-Bit Level Pipelined Multiplier Macrocell. VLSI Design Debabrata Ghosh, Shamik Sural, S. K. Nandy
1994	Misc	`conf`	A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. VLSI Design G. N. Rathna, S. K. Nandy, K. Parthasarathy
1994	J	`jnl`	Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment. VLSI Design S. K. Nandy
1994	J	`jnl`	Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors. VLSI Design S. K. Nandy, R. B. Panwar
1994	Misc	`conf`	High Speed Digital Filtering on SRAM-Based FPGAs. VLSI Design Abhijit Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal
1994	Misc	`conf`	TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. VLSI Design Debabrata Ghosh, S. K. Nandy, K. Parthasarathy
1993	C	`conf`	A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology. ICCD Debabrata Ghosh, S. K. Nandy
1993	—	`conf`	A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. ICPP (3) S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan
1993	A*	`conf`	Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. DAC Debabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy
1993	Misc	`conf`	NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. VLSI Design Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan
1990	J	`jnl`	Quasi dynamic approach to layout compaction. Microprocessing and Microprogramming S. Balakrishnan, S. K. Nandy
1990	J	`jnl`	VOXEL based modeling and rendering irregular solids. Microprocessing and Microprogramming C. E. Prakash, S. K. Nandy
1989	A*	`conf`	Special Purpose Architecture for Accelerating Bitmap DRC. DAC Narasimha B. Bhat, S. K. Nandy
1986	A*	`conf`	Dual quadtree representation for VLSI designs. DAC S. K. Nandy, L. V. Ramakrishnan