S. K. Manhas

18 papers Misc 2Journal 8Unranked 8
YearRankTypeTitle / Venue / Authors
2016 — conf
A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation.
VDAT
Om. Prakash, Satish Maheshwaram, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas
2016 J jnl
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization.
Microelectron. J.
Baljit Kaur, Arvind Kumar Sharma, Naushad Alam, S. K. Manhas, Bulusu Anand
2016 Misc conf
FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay.
VLSID
Archana Pandey, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, S. K. Manhas, Anand Bulusu
2016 — conf
Lateral silicon nanowire based standard cell design for higher performance.
APCCAS
Om. Prakash, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas, Satish Maheshwaram
2016 Misc conf
Metal Carbon Nanotube Schottky Barrier Diode with Detection of Polar Non-polar Gases.
VLSID
Sarvesh Agarwal, S. K. Manhas, Sudeb Dasgupta, Neeraj Jain
2015 J jnl
An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applications.
Microelectron. J.
Ashish Joshi, S. K. Manhas, Satinder K. Sharma, Sudeb Dasgupta
2015 J jnl
Low power SRAM design for 14 nm GAA Si-nanowire technology.
Microelectron. J.
Gaurav Kaushal, H. Jeong, Satish Maheshwaram, S. K. Manhas, Sudeb Dasgupta, Seong-Ook Jung
2014 J jnl
Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability.
IEEE Trans. Circuits Syst. I Regul. Pap.
Baljit Kaur, Naushad Alam, S. K. Manhas, Bulusu Anand
2013 — conf
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies.
ISQED
Baljit Kaur, Sandeep Miryala, S. K. Manhas, Bulusu Anand
2012 — conf
An accurate current source model for CMOS based combinational logic cell.
ISQED
Baljit Kaur, Sandeep Vundavalli, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand
2012 — conf
Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnects.
ISQED
Manoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas
2012 — conf
Comparison of crosstalk delay between single and bundled SWNT for global VLSI interconnects.
RAIT
Manoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas
2012 — conf
Propagation Delay Analysis for Bundled Multi-Walled CNT in Global VLSI Interconnects.
SocProS
Pankaj Kumar Das, Manoj Kumar Majumder, Brajesh Kumar Kaushik, S. K. Manhas
2011 J jnl
Barrier layer thickness analysis for reliable copper plug process in CMOS technology.
Microelectron. Reliab.
S. K. Manhas, N. Singh, G. Q. Lo
2010 — conf
A high performance vertical Si nanowire CMOS for ultra high density circuits.
APCCAS
Satish Maheshwaram, Gaurav Kaushal, S. K. Manhas
2004 J jnl
Influence of mobility model on extraction of stress dependent source-drain series resistance.
Microelectron. Reliab.
Merlyne M. De Souza, S. K. Manhas, D. Chandra Sekhar, A. S. Oates, Prasad Chaparala
2003 J jnl
Characterisation of series resistance degradation through charge pumping technique.
Microelectron. Reliab.
S. K. Manhas, D. Chandra Sekhar, A. S. Oates, Merlyne M. De Souza
2001 J jnl
A comparison of early stage hot carrier degradation behaviour in 5 and 3 V sub-micron low doped drain metal oxide semiconductor field effect transistors.
Microelectron. Reliab.
Merlyne M. De Souza, J. Wang, S. K. Manhas, E. M. Sankara Narayanan, A. S. Oates