S. Dasgupta

23 papers A* 1C 3Misc 1Journal 4Unranked 14
YearRankTypeTitle / Venue / Authors
2024 — conf
Self-Heating and Process-Induced Threshold Voltage Aware Reliability and Aging Analysis of Forksheet FET.
IRPS
Sunil Rathore, Navjeet Bagga, S. Dasgupta
2024 — conf
Small Signal Analysis of Nanosheet Transistor for sub-THz Frequency Considering Intersheet Capacitances and Modified Admittance Parameters.
DRC
Jyoti Patel, Navjeet Bagga, Vivek Kumar, S. Dasgupta
2015 — conf
A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives.
ISQED
Pankaj Kumar Pal, Brajesh Kumar Kaushik, B. Anand, S. Dasgupta
2015 — conf
Sensitivity analysis of DRV for various configurations of SRAM.
VDAT
Ruchi, S. Dasgupta
2015 — conf
Trapping characteristics and parametric shifts in lateral GaN HEMTs with SiO2/AlGaN gate stacks.
IRPS
M. P. King, Jeramy Ray Dickerson, S. Dasgupta, Matthew J. Marinella, R. J. Kaplar, Daniel Piedra, Min Sun, Tomás Palacios
2014 — conf
High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications.
VDAT
Dilsukh Nehra, Pankaj Kumar Pal, Brajesh Kumar Kaushik, S. Dasgupta
2014 J jnl
Sinusoidal Clocked Sense-amplifier-Based Energy Recovery flip-Flops.
J. Circuits Syst. Comput.
Jitendra Kanungo, S. Dasgupta
2013 J jnl
Energy estimation for n-input Adiabatic Logic gate: a Proposed Analytical Model.
J. Circuits Syst. Comput.
Jitendra Kanungo, S. Dasgupta
2013 C conf
Picard's method to solve a system of biaffine equations and its application to pole placement.
CCA
Gopal Jee, S. Dasgupta
2011 J jnl
An Efficient Single Phase Adiabatic Logic and Its Application to Combinational and Sequential Design.
J. Low Power Electron.
Jitendra Kanungo, S. Dasgupta
2011 J jnl
Routing of asynchronous Clos networks.
IET Comput. Digit. Tech.
Wei Song, D. Edwards, Z. Liu, S. Dasgupta
2002 C conf
Exact Fuzzy Modeling and Optimal control of a Launch Vehicle in the atmospheric phase.
ICARCV
P. P. Mohanlal, M. R. Kaimal, S. Dasgupta
1998 — conf
CHDStd - application support for reusable hierarchical interconnect timing views.
ISPD
S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, Donald Cottrell, David Mallis, S. Dasgupta, Joseph Morrell, Amrich Chokhavtia
1998 — conf
Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis.
ASP-DAC
S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, Donald Cottrell, David Mallis, S. Dasgupta, Joseph Morrell, J. Sayah, R. Gupta, P. T. Patel, P. Adams
1998 — conf
Panel: Given that SEMATECH is levelling the semiconductor technology playing field, will corporate CAD (in particular, PD) tools continue to serve as enablers/differentiators of technology in the future? (panel).
ISPD
S. Dasgupta
1997 — conf
Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century.
ISPD
R. G. Bushroe, S. Dasgupta, A. Dengi, P. Fisher, S. Grout, G. Ledenbach, N. S. Nagaraj, R. Steele
1992 Misc conf
A Simple Model for Lindhard Continuum Potential useful for Channeling Simulation.
VLSI Design
R. Ghosh, S. Dasgupta
1990 — conf
Effect of data compression of ERP sign preprocessed by FWT algorithm upon a neural network classifier.
Annual Simulation Symposium
S. Dasgupta, M. Hohenberger, Len Trejo, T. Kaylani
1990 — conf
Optimization of a digital neuron design.
Annual Simulation Symposium
F. Kampf, P. Koch, K. Roy, M. Sullivan, Z. Delalic, S. Dasgupta
1989 C conf
Description Language for a Neural Network Architecture.
IAS
S. Dasgupta, Kalapi Roy
1989 — conf
Design of a general purpose meta-assembler for parallel processor environment in ISPS.
Annual Simulation Symposium
M. R. Brown, S. Dasgupta
1987 — conf
Simulation of a computer with variable hardware and variable instruction set.
Annual Simulation Symposium
S. Dasgupta, H. Chang
1986 A* conf
Tutorial on parallel processing for design automation applications (tutorial session).
DAC
J. M. Hancock, S. Dasgupta