Rémi Dekimpe

11 papers A 1C 1Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2025 — conf
Exploring the Direct and Indirect Environmental Impacts of Mobile Health - A Case Study on Continuous Glucose Monitoring.
ICT4S
Augustin Wattiez, Rémi Dekimpe, Thibault Pirson, David Bol
2024 J jnl
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rémi Dekimpe, David Bol
2023 J jnl
Technical and Ecological Limits of 2.45-GHz Wireless Power Transfer for Battery-Less Sensors.
IEEE Internet Things J.
Marco Gonzalez, Pengcheng Xu, Rémi Dekimpe, Maxime Schramme, Ivan Stupia, Thibault Pirson, David Bol
2022 J jnl
ECG Arrhythmia Classification on an Ultra-Low-Power Microcontroller.
IEEE Trans. Biomed. Circuits Syst.
Rémi Dekimpe, David Bol
2022 — conf
Mixed-Signal Compensation of Tripolar Cuff Electrode Imbalance in a Low-Noise ENG Analog Front-End.
ESSCIRC
Rémi Dekimpe, David Bol
2021 — conf
A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection.
ISSCC
Martin Lefebvre, Ludovic Moreau, Rémi Dekimpe, David Bol
2021 J jnl
A Configurable ULP Instrumentation Amplifier With Pareto-Optimal Power-Noise Trade-Off Achieving 1.93 NEF in 65nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Rémi Dekimpe, David Bol
2021 A conf
Moore's Law and ICT Innovation in the Anthropocene.
DATE
David Bol, Thibault Pirson, Rémi Dekimpe
2021 — conf
SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management.
VLSI Circuits
Rémi Dekimpe, Maxime Schramme, Martin Lefebvre, Adrian Kneip, Roghayeh Saeidi, Mathieu Xhonneux, Ludovic Moreau, Marco Gonzalez, Thibault Pirson, David Bol
2021 J jnl
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode.
IEEE J. Solid State Circuits
David Bol, Maxime Schramme, Ludovic Moreau, Pengcheng Xu, Rémi Dekimpe, Roghayeh Saeidi, Thomas Haine, Charlotte Frenkel, Denis Flandre
2019 C conf
A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells.
ISCAS
Ludovic Moreau, Rémi Dekimpe, David Bol