Régis Leveugle

153 papers A* 2A 10B 6C 43Misc 2Journal 19Unranked 71

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Embedded Tutorial: Design for EMC and Trust in Integrated Systems - Combining Robustness, Innocuity and Security Concerns. LATS Régis Leveugle
2026	—	`conf`	M-EL2N: Data-Efficient Fault Injection Through Sample Difficulty Analysis. LATS Nicolò Bellarmino, Alberto Bosio, Ahmed Al Kaf, Mounir Benabdenbi, Régis Leveugle, Riccardo Cantoro
2025	—	`conf`	Analysis of Voltage Drop and Temperature Effects on Harmonic Errors Under EMFI on ROs. LATS Sami El Amraoui, Luc Salvo, Régis Leveugle, Paolo Maistri
2025	—	`conf`	Edge AI Dependability: Is Bit-flip Direction the Right Concern in Trustworthiness Reinforcement? SBCCI Régis Leveugle, Ahmed Al Kaf, Mounir Benabdenbi
2025	—	`conf`	Embedded Tutorial: Integrated System Hardening Seen from a Security Point of View: Dream or Nightmare? LATS Régis Leveugle
2025	J	`jnl`	On the Harmonic Locking of Ring Oscillators under Single ElectroMagnetic Pulsed Fault Injection in FPGAs. J. Electron. Test. Sami El Amraoui, Aghiles Douadi, Régis Leveugle, Paolo Maistri
2025	C	`conf`	Pulsed ElectroMagnetic Fault Injection Attack on a Time Measurement-based Arbiter-PUF. DSD Azzadine Thajte, Sami El Amraoui, Paolo Maistri, Régis Leveugle, Giorgio Di Natale, Laurent Fesquet
2025	B	`conf`	Pulsed Electromagnetic Fault Injection Attack on Ring Oscillator-based PUFs in FPGAs. ETS Sami El Amraoui, Aghiles Douadi, Régis Leveugle, Paolo Maistri
2024	C	`conf`	Capture the Pulse: Impact of FPGA Resource Utilization on EM Fault Injection Attacks Detection. VLSI-SoC Sami El Amraoui, Régis Leveugle, Paolo Maistri
2024	—	`conf`	Challenges in FPGA Resource Allocation and Placement for Efficient EM Fault Attack Detection Strategies. VLSI-SoC (Selected Papers) Sami El Amraoui, Régis Leveugle, Paolo Maistri
2024	C	`conf`	Choose your Path: Control of Ring Oscillators EMFI Susceptibility through FPGA P&R Constraints. DDECS Sami El Amraoui, Régis Leveugle, Paolo Maistri
2024	—	`conf`	Combining Acceleration and Approximation in Dependable Edge AI: Optimization Methodology and Tools Applied to a Case Study. DTTIS Régis Leveugle, Mounir Benabdenbi, Ahmed Al Kaf, Luc Noizette
2024	—	`conf`	Harmonic Response of Ring Oscillators under Single ElectroMagnetic Pulsed Fault Injection. LATS Sami El Amraoui, Aghiles Douadi, Régis Leveugle, Paolo Maistri
2024	—	`conf`	Secured Bus as a Countermeasure against Covert Channels: NEORV32 Case Study. LATS Régis Leveugle, Nathan Hocquette, Charles Labarre, Romain Plumaugat, Loic Tcharoukian, Valentin Martinoli, Yannick Teglia
2024	—	`conf`	Using High-Level Profiling Data to Early Assess the Robustness of Digital Systems. DFT Luc Noizette, Florent Miller, Youri Helen, Régis Leveugle
2022	J	`jnl`	CVA6's Data cache: Structure and Behavior. CoRR Valentin Martinoli, Yannick Teglia, Abdellah Bouagoun, Régis Leveugle
2022	C	`conf`	Recovering Information on the CVA6 RISC-V CPU with a Baremetal Micro-Architectural Covert Channel. IOLTS Valentin Martinoli, Yannick Teglia, Abdellah Bouagoun, Régis Leveugle
2022	—	`conf`	Using Application Profiling based on a Virtual Platform for SoC Fault Tolerance Assessment. PRIME Luc Noizette, Florent Miller, Thierry Colladant, Youri Helen, Régis Leveugle
2021	C	`conf`	Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism. VLSI-SoC Julie Roux, Katell Morin-Allory, Vincent Beroulle, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier
2021	—	`conf`	FMEA on Critical Systems: A Cross-Layer Approach Based on High-Level Models. VLSI-SoC (Selected Papers) Julie Roux, Katell Morin-Allory, Vincent Beroulle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier, Régis Leveugle
2021	—	`conf`	Secure Test with RSNs: Seamless Authenticated Extended Confidentiality. NEWCAS Paolo Maistri, Vincent Reynaud, Michele Portolan, Régis Leveugle
2021	A	`conf`	Security EDA Extension through P1687.1 and 1687 Callbacks. ITC Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle, Giorgio Di Natale
2020	C	`conf`	A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. IOLTS Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel J. Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir
2020	C	`conf`	Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems. DDECS Julie Roux, Vincent Beroulle, Katell Morin-Allory, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier
2020	B	`conf`	Dynamic Authentication-Based Secure Access to Test Infrastructure. ETS Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle
2020	—	`conf`	High Level Fault Injection Method for Evaluating Critical System Parameter Ranges. ICECS Julie Roux, Vincent Beroulle, Katell Morin-Allory, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier
2019	—	`conf`	A Comprehensive Approach to a Trusted Test Infrastructure. IVSW Marc Merandat, Vincent Reynaud, Emanuele Valea, Jérôme Quévremont, Nicolas Valette, Paolo Maistri, Régis Leveugle, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre, Giorgio Di Natale
2019	B	`conf`	Alternatives to Fault Injections for Early Safety/Security Evaluations. ETS Michele Portolan, Alessandro Savino, Régis Leveugle, Stefano Di Carlo, Alberto Bosio, Giorgio Di Natale
2019	B	`conf`	Approximate computing design exploration through data lifetime metrics. ETS Alessandro Savino, Michele Portolan, Régis Leveugle, Stefano Di Carlo
2018	J	`jnl`	Hardware Support for Security in the Internet of Things: From Lightweight Countermeasures to Accelerated Homomorphic Encryption. Inf. Régis Leveugle, Asma Mkhinini, Paolo Maistri
2018	C	`conf`	Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model. FDTC Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Stephan De Castro, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hély, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
2018	C	`conf`	The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. IOLTS Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hély, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
2017	C	`conf`	HLS design of a hardware accelerator for Homomorphic Encryption. DDECS Asma Mkhinini, Paolo Maistri, Régis Leveugle, Rached Tourki
2017	C	`conf`	Reliability of computing systems: From flip flops to variables. IOLTS Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Régis Leveugle
2016	—	`conf`	A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption. IDT Asma Mkhinini, Paolo Maistri, Régis Leveugle, Rached Tourki, Mohsen Machhout
2016	J	`jnl`	Analysis of laser-induced errors: RTL fault models versus layout locality characteristics. Microprocess. Microsystems Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle
2016	J	`jnl`	Dummy operations in scalar multiplication over elliptic curves: A tradeoff between security and performance. Microprocess. Microsystems Simon Pontie, Paolo Maistri, Régis Leveugle
2016	C	`conf`	Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations. IOLTS K. Chibani, Michele Portolan, Régis Leveugle
2016	C	`conf`	HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic. DSD Simon Pontie, Alban Bourge, Adrien Prost-Boucle, Paolo Maistri, Olivier Muller, Régis Leveugle, Frédéric Rousseau
2016	—	`conf`	On fault injections for early security evaluation vs. laser-based attacks. IVSW Régis Leveugle, A. Chahed, Paolo Maistri, Athanasios Papadimitriou, David Hély, Vincent Beroulle
2016	A	`conf`	On the development of a new countermeasure based on a laser attack RTL fault model. DATE Charalampos Ananiadis, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle
2016	—	`conf`	Taking into account indirect jumps or calls in continuous control-flow checking. IDT Lydie Terras, Yannick Teglia, Michel Agoyan, Régis Leveugle
2016	—	`conf`	Tutorial 1: "New approaches towards early dependability evaluation of digital integrated systems". IDT Régis Leveugle
2015	—	`conf`	Polynomial multipliers for fully homomorphic encryption on FPGA. ReConFig C. Jayet-Griffon, Marie-Angela Cornelie, Paolo Maistri, Philippe Elbaz-Vincent, Régis Leveugle
2015	—	`conf`	Validation of RTL laser fault injection model with respect to layout information. HOST Athanasios Papadimitriou, Marios Tampas, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle
2014	A	`conf`	A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks. DATE Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle
2014	C	`conf`	An Elliptic Curve Crypto-Processor Secured by Randomized Windows. DSD Simon Pontie, Paolo Maistri, Régis Leveugle
2014	—	`conf`	Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options. ICECS K. Chibani, Salma Bergaoui, Michele Portolan, Régis Leveugle
2014	C	`conf`	Electromagnetic analysis and fault injection onto secure circuits. VLSI-SoC Paolo Maistri, Régis Leveugle, Lilian Bossuet, Alain Aubert, Viktor Fischer, Bruno Robisson, Nicolas Moro, Philippe Maurine, Jean-Max Dutertre, Mathieu Lisart
2014	—	`conf`	Electromagnetic attacks on embedded devices: A model of probe-circuit power coupling. DTIS Diego Alberto, Paolo Maistri, Régis Leveugle
2014	C	`conf`	Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor. VLSI-SoC K. Chibani, Mohamed Ben Jrad, Michele Portolan, Régis Leveugle
2014	—	`conf`	IDSM: An improved disjoint signature monitoring scheme for processor behavioral checking. LATW Salma Bergaoui, Pierre Vanhauwaert, Régis Leveugle
2014	—	`conf`	Laser-Induced Fault Effects in Security-Dedicated Circuits. VLSI-SoC (Selected Papers) Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre, Marie-Lise Flottes, David Hély, Guillaume Hubert, Régis Leveugle, Feng Lu, Paolo Maistri, Athanasios Papadimitriou, Bruno Rouzeyre, Clément Tavernier, Pierre Vanhauwaert
2014	C	`conf`	Laser-induced fault effects in security-dedicated circuits. VLSI-SoC Régis Leveugle, Paolo Maistri, Pierre Vanhauwaert, Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Guillaume Hubert, Stephan De Castro, Jean-Max Dutertre, Alexandre Sarafianos, Noemie Boher, Mathieu Lisart, Joel Damiens, Philippe Candelier, Clément Tavernier
2014	—	`conf`	On error models for RTL security evaluations. DTIS Pierre Vanhauwaert, Paolo Maistri, Régis Leveugle, Athanasios Papadimitriou, David Hély, Vincent Beroulle
2013	—	`conf`	An evaluation of an AES implementation protected against EM analysis. ACM Great Lakes Symposium on VLSI Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle
2013	—	`conf`	Automated design flow for no-cost configuration error detection in sram-based FPGAs. ReConFig Mohamed Ben Jrad, Régis Leveugle
2013	—	`conf`	Countermeasures against EM analysis for a secured FPGA-based AES implementation. ReConFig Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle
2013	J	`jnl`	Detailed Analysis of Compilation Options for Robust Software-based Embedded Systems. J. Electron. Test. Salma Bergaoui, A. Wecxsteen, Régis Leveugle
2013	C	`conf`	Evaluating a low cost robustness improvement in SRAM-based FPGAs. IOLTS Mohamed Ben Jrad, Régis Leveugle
2013	J	`jnl`	Forecasting the Effects of Electromagnetic Fault Injections on Embedded Cryptosystems. Inf. Secur. J. A Glob. Perspect. Diego Alberto, Paolo Maistri, Régis Leveugle
2012	—	`conf`	Detailed analysis of compilation options for robust software-based embedded systems. LATW A. Wecxsteen, Salma Bergaoui, Régis Leveugle
2012	—	`conf`	Pattern-based injections in processors implemented on SRAM-based FPGAs. LATW Mohamed Ben Jrad, Régis Leveugle
2011	C	`conf`	10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard. DSD Paolo Maistri, Régis Leveugle
2011	J	`jnl`	Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. J. Cryptol. Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière, Florent Valette, Marc Renaudin
2011	—	`conf`	Impact of Software Optimization on Variable Lifetimes in a Microprocessor-Based System. DELTA Salma Bergaoui, Régis Leveugle
2011	B	`conf`	Towards Robustness Analysis Using PVS. ITP Renaud Clavel, Laurence Pierre, Régis Leveugle
2010	—	`conf`	A new methodology for accurate predictive robustness analysis of designs implemented in SRAM-based FPGAs. ICECS Régis Leveugle, Mohamed Ben Jrad
2010	—	`conf`	Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. ASAP Gaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin
2010	C	`conf`	Early Robustness Evaluation of Digital Integrated Systems. FDL Régis Leveugle
2010	B	`conf`	Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. ETS Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin
2009	Misc	`conf`	Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. VTS Gaetan Canivet, Régis Leveugle, Jessy Clédière, Frédéric Valette, Marc Renaudin
2009	—	`conf`	Complementary Formal Approaches for Dependability Analysis. DFT Souheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud
2009	A	`conf`	Statistical fault injection: Quantified error and confidence. DATE Régis Leveugle, A. Calvez, Paolo Maistri, Pierre Vanhauwaert
2009	C	`conf`	Towards automated fault pruning with Petri Nets. IOLTS Paolo Maistri, Régis Leveugle
2008	—	`conf`	Chip level security: Why ? How ? ICECS Régis Leveugle
2008	C	`conf`	Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. IOLTS Gaetan Canivet, Jessy Clédière, Jean Baptiste Ferron, Frédéric Valette, Marc Renaudin, Régis Leveugle
2008	J	`jnl`	Double-Data-Rate Computation as a Countermeasure against Fault Analysis. IEEE Trans. Computers Paolo Maistri, Régis Leveugle
2008	—	`conf`	Software BIST capabilities of a symmetric cipher. ICECS Paolo Maistri, Cyril Excoffon, Régis Leveugle
2008	C	`conf`	Software Self-Testing of a Symmetric Cipher with Error Detection Capability. IOLTS Paolo Maistri, Cyril Excoffon, Régis Leveugle
2008	—	`conf`	Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system. ICECS Pierre Vanhauwaert, Michele Portolan, Régis Leveugle, Philippe Roche
2007	C	`conf`	A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection. FDTC Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle
2007	J	`jnl`	CNTFET Modeling and Reconfigurable Logic-Circuit Design. IEEE Trans. Circuits Syst. I Regul. Pap. Ian O'Connor, Junchen Liu, Frédéric Gaffiot, Fabien Prégaldiny, Christophe Lallement, Cristell Maneux, Johnny Goguet, Sébastien Fregonese, Thomas Zimmer, Lorena Anghel, Trong-Trinh Dang, Régis Leveugle
2007	J	`jnl`	Configuration errors analysis in SRAM-based FPGAs: Software tool and practical results. Microelectron. Reliab. V. Maingot, Jean Baptiste Ferron, Régis Leveugle, Vincent Pouget, Alexandre Douin
2007	—	`conf`	Dependability issues in SRAM-based FPGA design. ICECS Régis Leveugle
2007	J	`jnl`	Early Analysis of Fault-based Attack Effects in Secure Circuits. IEEE Trans. Computers Régis Leveugle
2007	—	`conf`	Effective Checkpoint and Rollback Using Hardware/OS Collaboration. DFT Michele Portolan, Régis Leveugle
2007	—	`conf`	Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections. DFT Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle
2007	A	`conf`	Experimental evaluation of protections against laser-induced faults and consequences on fault modeling. DATE Régis Leveugle, Abdelaziz Ammari, V. Maingot, E. Teyssou, Pascal Moitrel, Christophe Mourtel, Nathalie Feyt, Jean-Baptiste Rigaud, Assia Tria
2007	C	`conf`	Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. IOLTS Yannick Monnet, Marc Renaudin, Régis Leveugle
2007	—	`conf`	On Deratings to Refine System-Level Failure Rate Estimations. ICECS Christophe Smekens, Régis Leveugle
2006	C	`conf`	A Flexible SoPC-based Fault Injection Environment. DDECS Pierre Vanhauwaert, Régis Leveugle, Philippe Roche
2006	C	`conf`	Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. FDTC Yannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel
2006	J	`jnl`	Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. IEEE Trans. Computers Yannick Monnet, Marc Renaudin, Régis Leveugle
2006	—	`conf`	Error Detection Code Efficiency for Secure Chips. ICECS Vincent Maingot, Régis Leveugle
2006	—	`conf`	Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection. DELTA Abdelaziz Ammari, Régis Leveugle, Bogdan Nicolescu, Yvon Savaria
2006	C	`conf`	On the Use of Information Redundancy When Designing Secure Chips. DDECS Régis Leveugle, V. Maingot
2006	C	`conf`	Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. IOLTS Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet
2006	C	`conf`	Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis. VLSI-SoC Pierre Vanhauwaert, Régis Leveugle, Philippe Roche
2005	C	`conf`	A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations. IOLTS Régis Leveugle
2005	A*	`conf`	Asynchronous circuits transient faults sensitivity evaluation. DAC Yannick Monnet, Marc Renaudin, Régis Leveugle
2005	J	`jnl`	Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation. J. Electron. Test. Abdelaziz Ammari, K. Hadjiat, Régis Leveugle
2005	C	`conf`	Evaluation of SET and SEU Effects at Multiple Abstraction Levels. IOLTS Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert
2005	C	`conf`	Hardening Techniques against Transient Faults for Asynchronous Circuits. IOLTS Yannick Monnet, Marc Renaudin, Régis Leveugle
2005	C	`conf`	Introduction to the Special Session on Secure Implementations. IOLTS Régis Leveugle
2005	C	`conf`	On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. IOLTS Michele Portolan, Régis Leveugle
2005	C	`conf`	On-Line Testing for Secure Implementations: Design and Validation. IOLTS Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert
2005	C	`conf`	Towards a Secure and Reliable System. EUC Michele Portolan, Régis Leveugle
2004	C	`conf`	Asynchronous Circuits Sensitivity to Fault Injection. IOLTS Yannick Monnet, Marc Renaudin, Régis Leveugle
2004	A	`conf`	Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow. DATE Régis Leveugle, Abdelaziz Ammari
2004	C	`conf`	On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation. IOLTS Abdelaziz Ammari, K. Hadjiat, Régis Leveugle
2004	C	`conf`	Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. IOLTS Michele Portolan, Régis Leveugle
2004	—	`conf`	System-Level Dependability Analysis with RT-Level Fault Injection Accuracy. DFT Régis Leveugle, D. Cimonnet, Abdelaziz Ammari
2003	A	`conf`	Dependability Analysis: A New Application for Run-Time Reconfiguration. IPDPS Régis Leveugle, Lörinc Antoni, Béla Fehér
2003	—	`conf`	Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. DFT Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante
2003	J	`jnl`	Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments. J. Electron. Test. Régis Leveugle, K. Hadjiat
2003	J	`jnl`	Special section on defect and fault tolerance in VLSI systems. Microelectron. J. Régis Leveugle, Glenn H. Chapman
2003	J	`jnl`	Using run-time reconfiguration for fault injection applications. IEEE Trans. Instrum. Meas. Lörinc Antoni, Régis Leveugle, Béla Fehér
2002	A	`conf`	Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance. DATE Régis Leveugle
2002	—	`conf`	Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study. IOLTW Régis Leveugle, K. Hadjiat
2002	—	`conf`	Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. DFT Lörinc Antoni, Régis Leveugle, Béla Fehér
2001	—	`conf`	A Low-Cost Hardware Approach to Dependability Validation of Ips. DFT Régis Leveugle
2001	—	`conf`	High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance. DFT Régis Leveugle, R. Cercueil
2001	—	`conf`	Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results. DFT Raoul Velazco, Régis Leveugle, Oscar Calvo
2000	—	`conf`	Fault Injection in VHDL Descriptions and Emulation. DFT Régis Leveugle
2000	—	`conf`	Optimized Generation of VHDL Mutants for Injection of Transition Errors. SBCCI Régis Leveugle, K. Hadjiat
2000	—	`conf`	Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. DFT Lörinc Antoni, Régis Leveugle, Béla Fehér
1999	—	`conf`	Experiments on Multimedia Support of VLSI Design teaching in the MODEM Project. MSE Alejandro Chagoya, Régis Leveugle
1997	—	`conf`	Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities. DFT X. Wendling, H. Chauvet, Lionel Revéret, Raphaël Rochet, Régis Leveugle
1996	—	`conf`	ROM-Based Synthesis of Fault-Tolerant Controllers. DFT X. Wendling, Raphaël Rochet, Régis Leveugle
1996	Misc	`conf`	Standard and ROM-based synthesis of FSMs with control flow checking capabilities. VTS X. Wendling, Raphaël Rochet, Régis Leveugle
1995	—	`conf`	Design of defect-tolerant scan chains for MCMs with an active substrate. DFT P. Brahic, Régis Leveugle, Gabriele Saucier
1995	—	`conf`	Efficient synthesis of fault-tolerant controllers. ED&TC Raphaël Rochet, Régis Leveugle, Gabriele Saucier
1994	—	`conf`	Alternative Approaches to Fault Detection in FSMs. DFT Régis Leveugle, Raphaël Rochet, Gabriele Saucier
1994	—	`conf`	Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. EDAC-ETC-EUROASIC T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier
1994	—	`conf`	Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. EDAC-ETC-EUROASIC C. Safinia, Régis Leveugle, Gabriele Saucier
1994	J	`jnl`	The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis. IEEE Trans. Computers Régis Leveugle, Zahava Koren, Israel Koren, Gabriele Saucier, Norbert Wehn
1993	—	`conf`	A Synthesis Tool for Fault-Tolerant Finite State Machines. FTCS Régis Leveugle, Raphaël Rochet, Gabriele Saucier, L. Martinez, C. Pitot
1993	—	`conf`	Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. DFT Raphaël Rochet, Régis Leveugle, Gabriele Saucier
1993	C	`conf`	Influence of Error Correlations on the Signature Analysis Aliasing. ICCD Régis Leveugle, X. Delord, Gabriele Saucier
1993	A*	`conf`	Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes. DAC Régis Leveugle
1993	—	`conf`	Test of single fault tolerant controllers in VLSI circuits. VLSI Régis Leveugle
1992	—	`conf`	Clocking scheme selection for circuits made up of a controller and a datapath. Synthesis for Control Dominated Circuits C. Safina, Régis Leveugle
1992	—	`conf`	Generation of optimized datapaths: bit-slice versus standard cells. Synthesis for Control Dominated Circuits Régis Leveugle, C. Safina
1992	—	`conf`	Logic Synthesis for Automatic Layout. Synthesis for Control Dominated Circuits Pierre Abouzeid, Régis Leveugle, Gabriele Saucier
1992	—	`conf`	Synthesis of large controllers using ROM or PLA generators. Synthesis for Control Dominated Circuits Laurent Gerbaux, Régis Leveugle, Gabriele Saucier
1991	—	`conf`	A New Approach to Control Flow Checking Without Program Modification. FTCS T. Michel, Régis Leveugle, Gabriele Saucier
1991	A	`conf`	Hierarchical Test Generation Based on Delayed Propagation. ITC Margot Karam, Régis Leveugle, Gabriele Saucier
1990	—	`conf`	Design of microprocessors with built-in on-line test. FTCS Régis Leveugle, T. Michel, Gabriele Saucier
1990	J	`jnl`	Optimized Synthesis of Concurrently Checked Controllers. IEEE Trans. Computers Régis Leveugle, Gabriele Saucier
1989	C	`conf`	A channelless layout for multilevel synthesis with compiled cells. ICCD Gabriele Saucier, Régis Leveugle, Pierre Abouzeid
1989	C	`conf`	Concurrent checking in dedicated controllers. ICCD Régis Leveugle, Gabriele Saucier
1989	A	`conf`	Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. ITC Régis Leveugle, Gabriele Saucier