Ryuta Kawano

17 papers B 2C 3Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2022 J jnl
A traffic-aware memory-cube network using bypassing.
Microprocess. Microsystems
Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi
2022 — conf
Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks.
CANDAR
Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2021 — conf
GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph.
ACIT
Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2021 C conf
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths.
PDP
Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi
2020 J jnl
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks.
IEICE Trans. Inf. Syst.
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2020 — conf
Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks.
CANDAR (Workshops)
Ryuta Kawano, Hiroki Matsutani, Hideharu Amano
2020 J jnl
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks.
IEICE Trans. Inf. Syst.
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2019 — conf
Deadlock-Free Layered Routing for Infiniband Networks.
CANDAR Workshops
Ryuta Kawano, Hiroki Matsutani, Hideharu Amano
2018 — conf
k-Optimized Path Routing for High-Throughput Data Center Networks.
CANDAR
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano
2017 J jnl
A Layout-Oriented Routing Method for Low-Latency HPC Networks.
IEICE Trans. Inf. Syst.
Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2017 J jnl
A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing.
IEICE Trans. Inf. Syst.
Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2017 J jnl
Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator.
IEICE Trans. Inf. Syst.
Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano
2017 B conf
HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies.
ICPADS
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2016 C conf
ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free.
ICIS
Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2016 B conf
Body bias grain size exploration for a coarse grained reconfigurable accelerator.
FPL
Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano
2016 — conf
LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies.
CANDAR
Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2015 C conf
Optimized Core-Links for Low-Latency NoCs.
PDP
Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi