Ryusuke Nebashi

19 papers B 1C 2Journal 9Unranked 7

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	28nm Atom-Switch FPGA: Static Timing Analysis and Evaluation. IEICE Trans. Electron. Xu Bai, Ryusuke Nebashi, Makoto Miyamura, Kazunori Funahashi, Naoki Banno, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada
2022	J	`jnl`	Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation. IEEE J. Solid State Circuits Xu Bai, Naoki Banno, Makoto Miyamura, Ryusuke Nebashi, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Masanori Hashimoto, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada
2020	B	`conf`	A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS. FPL Ryusuke Nebashi, Naoki Banno, Makoto Miyamura, Xu Bai, Kazunori Funahashi, Koichiro Okamoto, Noriyuki Iguchi, Hideaki Numata, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada
2020	—	`conf`	ON-state retention of Atom Switch eNVM for IoT/AI Inference Solution. IRPS Koichiro Okamoto, Ryusuke Nebashi, Naoki Banno, Xu Bai, Hideaki Numata, Noriyuki Iguchi, Makoto Miyamura, Hiromitsu Hada, Kazunori Funahashi, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada
2017	J	`jnl`	NanoBridge-Based FPGA in High-Temperature Environments. IEEE Micro Makoto Miyamura, Toshitsugu Sakamoto, Xu Bai, Yukihide Tsuji, Ayuka Morioka, Ryusuke Nebashi, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada, Tadahiko Sugibayashi, Yuya Nagamatsu, Soichi Ookubo, Takuma Shirai, Fumihito Sugai, Masayuki Inaba
2016	—	`conf`	A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond. VLSI Circuits Yukihide Tsuji, Xu Bai, Ayuka Morioka, Makoto Miyamura, Ryusuke Nebashi, Toshitsugu Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada, Tadahiko Sugibayashi
2016	J	`jnl`	Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory. J. Multiple Valued Log. Soft Comput. Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
2015	J	`jnl`	Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014	—	`conf`	10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. ISSCC Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi
2014	C	`conf`	A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. ISCAS Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi
2014	J	`jnl`	Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014	—	`conf`	Soft-Delay-Error Evaluation in Content-Addressable Memory. ISMVL Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
2013	—	`conf`	Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2012	C	`conf`	High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2009	—	`conf`	A 90nm 12ns 32Mb 2T1MTJ MRAM. ISSCC Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito, Yuichi Ito, Sadahiko Miura, Yuko Kato, Kaoru Mori, Yasuaki Ozaki, Yosuke Kobayashi, Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Katsumi Suemitsu, Shunsuke Fukami, Hiromitsu Hada, Tadahiko Sugibayashi, Naoki Kasai
2009	J	`jnl`	Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs. IEEE J. Solid State Circuits Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai
2009	J	`jnl`	Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros. IEICE Trans. Electron. Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai
2008	—	`conf`	Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs. CICC Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai
2007	J	`jnl`	A 16-Mb Toggle MRAM With Burst Modes. IEEE J. Solid State Circuits Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Katsumi Suemitsu, Tomonori Mukai, Kaoru Mori, Ryusuke Nebashi, Shunsuke Fukami, Norikazu Ohshima, Hiromitsu Hada, Nobuyuki Ishiwata, Naoki Kasai, Shuichi Tahara