Ryuichi Fujimoto

46 papers C 1Journal 29Unranked 16

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Accelerating CNN Inference with an Adaptive Quantization Method Using Computational Complexity-Aware Regularization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kengo Nakata, Daisuke Miyashita, Jun Deguchi, Ryuichi Fujimoto
2025	J	`jnl`	Quantization Strategy for Achieving Low-Cost, Accurate, Pareto-Optimal Convolutional Neural Networks Based on Analysis of Quantized Weight Parameters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kengo Nakata, Daisuke Miyashita, Asuka Maki, Fumihiko Tachibana, Shinichi Sasaki, Jun Deguchi, Ryuichi Fujimoto
2024	J	`jnl`	Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryuichi Fujimoto
2022	J	`jnl`	A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. IEEE J. Solid State Circuits Takashi Toi, Junji Wadatsumi, Hiroyuki Kobayashi, Yutaka Shimizu, Yuji Satoh, Makoto Morimoto, Rui Ito, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Go Urakawa, Jun Deguchi, Ryuichi Fujimoto
2021	J	`jnl`	A Noise-Canceling Charge Pump for Area Efficient PLL Design. IEICE Trans. Electron. Go Urakawa, Hiroyuki Kobayashi, Jun Deguchi, Ryuichi Fujimoto
2021	C	`conf`	Adaptive Quantization Method for CNN with Computational-Complexity-Aware Regularization. ISCAS Kengo Nakata, Daisuke Miyashita, Jun Deguchi, Ryuichi Fujimoto
2021	—	`conf`	Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN. AICAS Kengo Nakata, Daisuke Miyashita, Asuka Maki, Fumihiko Tachibana, Shinichi Sasaki, Jun Deguchi, Ryuichi Fujimoto
2020	J	`jnl`	Weight Compression MAC Accelerator for Effective Inference of Deep Learning. IEICE Trans. Electron. Asuka Maki, Daisuke Miyashita, Shinichi Sasaki, Kengo Nakata, Fumihiko Tachibana, Tomoya Suzuki, Jun Deguchi, Ryuichi Fujimoto
2019	J	`jnl`	A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems. IEEE J. Solid State Circuits Yuta Tsubouchi, Daisuke Miyashita, Takashi Toi, Yuji Satoh, Fumihiko Tachibana, Junji Wadatsumi, Makoto Morimoto, Ryuichi Fujimoto, Jun Deguchi
2018	—	`conf`	Performance Evaluation of Age Estimation from T1-Weighted Images Using Brain Local Features and CNN. EMBC Koichi Ito, Ryuichi Fujimoto, Tzu-Wei Huang, Hwann-Tzong Chen, Kai Wu, Kazunori Sato, Yasuyuki Taki, Hiroshi Fukuda, Takafumi Aoki
2017	—	`conf`	A low voltage 0.8V RF receiver in 28nm CMOS for 5GHz WLAN. ESSCIRC Atsushi Shirane, Shusuke Kawai, Hiromitsu Aoyama, Rui Ito, Toshiya Mitomo, Hiroyuki Kobayashi, Hiroshi Yoshida, Hideaki Majima, Ryuichi Fujimoto, Hiroshi Tsurumi
2017	—	`conf`	Age estimation from brain MRI images using deep learning. ISBI Tzu-Wei Huang, Hwann-Tzong Chen, Ryuichi Fujimoto, Koichi Ito, Kai Wu, Kazunori Sato, Yasuyuki Taki, Hiroshi Fukuda, Takafumi Aoki
2017	J	`jnl`	An 18 µW Spur Cancelled Clock Generator for Recovering Receiver Sensitivity in Wireless SoCs. IEICE Trans. Electron. Yosuke Ogasawara, Ryuichi Fujimoto, Tsuneo Suzuki, Kenichi Sami
2017	—	`conf`	Brain age estimation from T1-weighted images using effective local features. EMBC Ryuichi Fujimoto, Koichi Ito, Kai Wu, Kazunori Sato, Yasuyuki Taki, Hiroshi Fukuda, Takafumi Aoki
2016	—	`conf`	Age estimation using effective brain local features from T1-weighted images. EMBC Ryuichi Fujimoto, Chihiro Kondo, Koichi Ito, Kai Wu, Kazunori Sato, Yasuyuki Taki, Hiroshi Fukuda, Takafumi Aoki
2016	—	`conf`	All-digital single-inductor multiple-output DC-DC converter with over 65.3% efficiency in 1 uW to 50 mW load range and 86.3% peak efficiency. A-SSCC Manabu Yamada, Nam Binh Tran, Takayuki Miyazaki, Yoshiaki Yoshihara, Ryuichi Fujimoto
2016	—	`conf`	An 18 µW spur canceled clock generator for recovering receiver sensitivity in wireless SoCs. VLSI Circuits Yosuke Ogasawara, Hiroki Sakurai, Ryuichi Fujimoto, Kenichi Sami
2016	J	`jnl`	Analog and Digital Collaborative Design Techniques for Wireless SoCs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryuichi Fujimoto
2014	—	`conf`	3D-integrated, low-height, small module design techniques for 4.48GHz, 560MHz-bandwidth TransferJet™ transceiver. RWS Kenichi Agawa, Ichiro Seto, Akihiko Happoya, Yoshihiro Iida, Yusuke Imaizumi, Motochika Okano, Daigo Suzuki, Yuichi Sato, Masaomi Iwanaga, Kazumi Sato, Satoshi Arai, Noriaki Uchida, Koji Ryugo, Daisuke Miyashita, Ryuichi Fujimoto, Yasuo Unekawa
2014	—	`conf`	A 0.171-mW, 2.4-GHz Class-D VCO with dynamic supply voltage control. ESSCIRC Yoshiaki Yoshihara, Hideaki Majima, Ryuichi Fujimoto
2013	—	`conf`	14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers. RWS Kyoya Takano, Ryuichi Fujimoto, Mizuki Motoyoshi, Kosuke Katayama, Minoru Fujishima
2013	J	`jnl`	98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits. IEEE J. Solid State Circuits Minoru Fujishima, Mizuki Motoyoshi, Kosuke Katayama, Kyoya Takano, Naoko Ono, Ryuichi Fujimoto
2013	J	`jnl`	A -70 dBm-Sensitivity 522 Mbps 0.19 nJ/bit-TX 0.43 nJ/bit-RX Transceiver for TransferJet IEICE Trans. Electron. Daisuke Miyashita, Kenichi Agawa, Hirotsugu Kajihara, Kenichi Sami, Ichiro Seto, Ryuichi Fujimoto, Yasuo Unekawa
2013	J	`jnl`	A 120 GHz/140 GHz Dual-Channel OOK Receiver Using 65 nm CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryuichi Fujimoto, Mizuki Motoyoshi, Kyoya Takano, Minoru Fujishima
2013	J	`jnl`	Foreword. IEICE Trans. Electron. Ryuichi Fujimoto
2012	—	`conf`	135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS. VLSIC Naoko Ono, Mizuki Motoyoshi, Kyoya Takano, Kosuke Katayama, Ryuichi Fujimoto, Minoru Fujishima
2012	—	`conf`	A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS. VLSIC Daisuke Miyashita, Kenichi Agawa, Hirotsugu Kajihara, Kenichi Sami, Masaomi Iwanaga, Yosuke Ogasawara, Tomohiko Ito, Daisuke Kurose, Naotaka Koide, Toru Hashimoto, Hiroki Sakurai, Takafumi Yamaji, Takashi Kurihara, Kazumi Sato, Ichiro Seto, Hiroshi Yoshida, Ryuichi Fujimoto, Yasuo Unekawa
2012	J	`jnl`	A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology. IEICE Trans. Electron. Ryuichi Fujimoto, Mizuki Motoyoshi, Kyoya Takano, Uroschanit Yodprasit, Minoru Fujishima
2012	J	`jnl`	A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter. IEICE Trans. Electron. Daisuke Miyashita, Hiroyuki Kobayashi, Jun Deguchi, Shouhei Kousai, Mototsugu Hamada, Ryuichi Fujimoto
2012	J	`jnl`	Bias-Voltage-Dependent Subcircuit Model for Millimeter-Wave CMOS Circuit. IEICE Trans. Electron. Kosuke Katayama, Mizuki Motoyoshi, Kyoya Takano, Ryuichi Fujimoto, Minoru Fujishima
2011	J	`jnl`	140GHz CMOS amplifier with group delay variation of 10.2ps and 0.1dB bandwidth of 12GHz. IEICE Electron. Express Mizuki Motoyoshi, Ryuichi Fujimoto, Kyoya Takano, Minoru Fujishima
2011	J	`jnl`	A Single-Chip RF Tuner/OFDM Demodulator for Mobile Digital TV Application. IEICE Trans. Electron. Yoshimitsu Takamatsu, Ryuichi Fujimoto, Tsuyoshi Sekine, Takaya Yasuda, Mitsumasa Nakamura, Takuya Hirakawa, Masato Ishii, Motohiko Hayashi, Hiroya Ito, Yoko Wada, Teruo Imayama, Tatsuro Oomoto, Yosuke Ogasawara, Masaki Nishikawa, Yoshihiro Yoshida, Kenji Yoshioka, Shigehito Saigusa, Hiroshi Yoshida, Nobuyuki Itoh
2011	J	`jnl`	Analysis of De-Embedding Error Cancellation in Cascade Circuit Design. IEICE Trans. Electron. Kyoya Takano, Ryuichi Fujimoto, Kosuke Katayama, Mizuki Motoyoshi, Minoru Fujishima
2011	J	`jnl`	Device Modeling Techniques for High-Frequency Circuits Design Using Bond-Based Design at over 100 GHz. IEICE Trans. Electron. Ryuichi Fujimoto, Kyoya Takano, Mizuki Motoyoshi, Uroschanit Yodprasit, Minoru Fujishima
2009	J	`jnl`	A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS. IEICE Trans. Electron. Hiroaki Hoshino, Ryoichi Tachibana, Toshiya Mitomo, Naoko Ono, Yoshiaki Yoshihara, Ryuichi Fujimoto
2009	—	`conf`	A single-chip RF tuner / OFDM demodulator for mobile digital TV application. ESSCIRC Tsuyoshi Sekine, Ryuichi Fujimoto, Yoshimitsu Takamatsu, Mitsumasa Nakamura, Takuya Hirakawa, Masato Ishii, Takaya Yasuda, Motohiko Hayashi, H. Itoh, Yoko Wada, Teruo Imayama, Tatsuro Oomoto, Yosuke Ogasawara, Shigehito Saigusa, M. Yano, Masaki Nishikawa, Hiroshi Yoshida, Yoshihiro Yoshida, Kenji Yoshioka, Nobuyuki Itoh
2008	J	`jnl`	A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer. IEEE J. Solid State Circuits Toshiya Mitomo, Ryuichi Fujimoto, Naoko Ono, Ryoichi Tachibana, Hiroaki Hoshino, Yoshiaki Yoshihara, Yukako Tsutsumi, Ichiro Seto
2008	J	`jnl`	A Low-Noise Amplifier for WCDMA Terminal with High Tolerance for Leakage Signal from Transmitter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryuichi Fujimoto, Gaku Takemura, Masato Ishii, Takehiko Toyoda, Hiroshi Tsurumi
2007	—	`conf`	A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS. ESSCIRC Hiroaki Hoshino, Ryoichi Tachibana, Toshiya Mitomo, Naoko Ono, Yoshiaki Yoshihara, Ryuichi Fujimoto
2007	J	`jnl`	A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage. IEICE Trans. Electron. Toshiya Mitomo, Osamu Watanabe, Ryuichi Fujimoto, Shunji Kawaguchi
2006	—	`conf`	A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage. CICC Toshiya Mitomo, Osamu Watanabe, Ryuichi Fujimoto, Shunji Kawaguchi
2005	J	`jnl`	A Direct Conversion Receiver for W-CDMA Reducing Current Consumption to 31 mA. IEICE Trans. Electron. Hiroshi Yoshida, Takehiko Toyoda, Makoto Arai, Ryuichi Fujimoto, Toshiya Mitomo, Masato Ishii, Rui Ito, Tadashi Arai, Tetsuro Itakura, Hiroshi Tsurumi
2005	J	`jnl`	A Low LO Leakage and Low Power LO Buffer for Direct-Conversion Quadrature Demodulator. IEICE Trans. Electron. Toshiya Mitomo, Osamu Watanabe, Shoji Otaka, Ryuichi Fujimoto, Shunji Kawaguchi
2002	J	`jnl`	A 7-GHz 1.8-dB NF CMOS low-noise amplifier. IEEE J. Solid State Circuits Ryuichi Fujimoto, Kenji Kojima, Shoji Otaka
1999	J	`jnl`	A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C filter IC. IEEE J. Solid State Circuits Tetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Akira Yasuda, Ryuichi Fujimoto, Tadashi Arai, Hideyuki Kokatsu
1996	J	`jnl`	A low local input 1.9 GHz Si-bipolar quadrature modulator with no adjustment. IEEE J. Solid State Circuits Shoji Otaka, Takafumi Yamaji, Ryuichi Fujimoto, Chikau Takahashi, Hiroshi Tanimoto