Ryota Yasudo

45 papers B 4C 2Misc 1Journal 18Unranked 20
YearRankTypeTitle / Venue / Authors
2026 J jnl
Memory-Efficient and Trustworthy Neural Networks via Random Seed-Based Design.
IEEE Access
Hiroaki Ito, Hikari Otsuka, Ryota Yasudo, Zhiqiang Que, José Gabriel F. Coutinho, Daichi Fujiki, Masato Motomura, Ce Guo, Wayne Luk
2026 J jnl
RL-driven Annealing Computation for QUBO on Multi-GPU System.
Int. J. Netw. Comput.
Reo Gakumi, Ryota Yasudo
2025 J jnl
A Scalable Accelerator for Local Score Computation of Structure Learning in Bayesian Networks.
ACM Trans. Reconfigurable Technol. Syst.
Ryota Miyagi, Ryota Yasudo, Kentaro Sano, Hideki Takase
2025 J jnl
Amorphica: A Fully Connected Annealer Supporting Metamorphic Annealing and Scalable Multi Chip Integration.
IEEE Access
Daiki Okonogi, Jaehoon Yu, Satoru Jimbo, Genta Inoue, Akira Hyodo, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
2025 J jnl
Photonic Ising Machine Using Parallel Bandit Architecture Based on Laser Chaos.
IEEE Access
Ryota Yasudo, Michihiro Koibuchi, Mikio Hasegawa
2025 — conf
RL-assisted Annealing for QUBO on a Multi-GPU System.
IPDPS (Workshops)
Reo Gakumi, Ryota Yasudo
2025 — conf
Trustworthy Deep Learning Acceleration with Customizable Design Flow Automation.
HEART
Zhiqiang Que, Hongxiang Fan, Gabriel F. Figueiredo, Ce Guo, Wayne Luk, Ryota Yasudo, Masato Motomura
2024 J jnl
A low-latency memory-cube network with dual diagonal mesh topology and bypassed pipelines.
Concurr. Comput. Pract. Exp.
Masashi Oda, Kai Keida, Ryota Yasudo
2024 J jnl
Power Optimized Design Framework for FPGA Clusters.
IPSJ Trans. Syst. LSI Des. Methodol.
Kensuke Iizuka, Kohei Ito, Ryota Yasudo, Hideharu Amano
2024 J jnl
Solving the QAP by Two-Stage Graph Pointer Networks and Reinforcement Learning.
CoRR
Satoko Iida, Ryota Yasudo
2023 — conf
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension.
ISSCC
Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura
2023 C conf
Bandit-based Variable Fixing for Binary Optimization on GPU Parallel Computing.
PDP
Ryota Yasudo
2023 J jnl
Designing low-diameter interconnection networks with multi-ported host-switch graphs.
Concurr. Comput. Pract. Exp.
Ryota Yasudo, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
2023 — conf
Dual Diagonal Mesh: An Optimal Memory Cube Network Under Geometric Constraints.
candar
Masashi Oda, Kai Keida, Ryota Yasudo
2023 J jnl
High-throughput FPGA implementation for quadratic unconstrained binary optimization.
Concurr. Comput. Pract. Exp.
Hiroshi Kagawa, Yasuaki Ito, Koji Nakano, Ryota Yasudo, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano
2023 — conf
Performance Modeling and Scalability Analysis of Stream Computing in ESSPER FPGA Clusters.
ICFPT
Ryota Miyagi, Ryota Yasudo, Kentaro Sano, Hideki Takase
2023 J jnl
Simple iterative trial search for the maximum independent set problem optimized for the GPUs.
Concurr. Comput. Pract. Exp.
Tomohiro Imanaga, Koji Nakano, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano
2022 — conf
Elastic Sample Filter: An FPGA-based Accelerator for Bayesian Network Structure Learning.
FPT
Ryota Miyagi, Ryota Yasudo, Kentaro Sano, Hideki Takase
2022 J jnl
GPU-accelerated scalable solver with bit permutated cyclic-min algorithm for quadratic unconstrained binary optimization.
J. Parallel Distributed Comput.
Ryota Yasudo, Koji Nakano, Yasuaki Ito, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano
2022 — conf
Graph-theoretic Formulation of QUBO for Scalable Local Search on GPUs.
IPDPS Workshops
Ryota Yasudo, Koji Nakano, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Shiro Ozaki, Takashi Yazane, Kenichiro Hamano
2022 B conf
Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches.
FPL
Kohei Ito, Ryota Yasudo, Hideharu Amano
2021 J jnl
Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms.
ACM Trans. Reconfigurable Technol. Syst.
Ryota Yasudo, José Gabriel de Figueiredo Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker, Ce Guo
2021 J jnl
Efficient implementations of Bloom filter using block RAMs and DSP slices on the FPGA.
Concurr. Comput. Pract. Exp.
Takuma Wada, Naoki Matsumura, Ryota Yasudo, Koji Nakano, Yasuaki Ito
2021 — conf
Solving the sparse QUBO on multiple GPUs for Simulating a Quantum Annealer.
CANDAR
Tomohiro Imanaga, Koji Nakano, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Shiro Ozaki, Takashi Yazane, Kenichiro Hamano
2020 J jnl
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks.
IEICE Trans. Inf. Syst.
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2020 — conf
A Work-Time Optimal Parallel Exhaustive Search Algorithm for the QUBO and the Ising model, with GPU implementation.
IPDPS Workshops
Masaki Tao, Koji Nakano, Yasuaki Ito, Ryota Yasudo, Masaru Tatekawa, Ryota Katsuki, Takashi Yazane, Yoko Inaba
2020 B conf
Adaptive Bulk Search: Solving Quadratic Unconstrained Binary Optimization Problems on Multiple GPUs.
ICPP
Ryota Yasudo, Koji Nakano, Yasuaki Ito, Masaru Tatekawa, Ryota Katsuki, Takashi Yazane, Yoko Inaba
2020 C conf
Dual-Plane Isomorphic Hypercube Network.
HPC Asia
Takeo Hosomi, Ryota Yasudo, Michihiro Koibuchi, Shinji Shimojo
2020 — conf
Efficient GPU Implementation for Solving the Maximum Independent Set Problem.
CANDAR
Tomohiro Imanaga, Koji Nakano, Masaki Tao, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano
2020 — conf
Fully-Pipelined Architecture for Simulated Annealing-based QUBO Solver on the FPGA.
CANDAR
Hiroshi Kagawa, Yasuaki Ito, Koji Nakano, Ryota Yasudo, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano
2020 J jnl
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks.
IEICE Trans. Inf. Syst.
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2019 J jnl
Designing High-Performance Interconnection Networks with Host-Switch Graphs.
IEEE Trans. Parallel Distributed Syst.
Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano
2019 — conf
Folded Bloom Filter for High Bandwidth Memory, with GPU Implementations.
CANDAR
Masatoshi Hayashikawa, Koji Nakano, Yasuaki Ito, Ryota Yasudo
2019 — conf
The Degree Diameter Problem for Host-Switch Graphs.
CANDAR Workshops
Ryota Yasudo, Koji Nakano
2018 — conf
Performance Estimation for Exascale Reconfigurable Dataflow Platforms.
FPT
Ryota Yasudo, José Gabriel F. Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker
2018 Misc conf
Performance Prediction for Large-Scale Heterogeneous Platforms.
FCCM
Ryota Yasudo, Ana Lucia Varbanescu, José Gabriel F. Coutinho, Wayne Luk, Hideharu Amano
2018 — conf
k-Optimized Path Routing for High-Throughput Data Center Networks.
CANDAR
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano
2017 — conf
3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface.
ISPAN-FCST-ISCC
Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2017 B conf
HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies.
ICPADS
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2017 B conf
Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks.
ICPP
Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano
2017 J jnl
Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers.
IEEE Trans. Computers
Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
2017 — conf
XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs.
NOCS
Hiroshi Nakahara, Ng. Anh Vu Doan, Ryota Yasudo, Hideharu Amano
2015 — conf
On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck.
NOCS
Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
2014 — conf
A low power NoC router using the marching memory through type.
COOL Chips
Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
2014 — conf
Design of a low power NoC router using Marching Memory Through type.
NOCS
Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura