Ryota Shioya

65 papers A* 4A 6B 4C 13Misc 1Journal 25Unranked 12
YearRankTypeTitle / Venue / Authors
2026 J jnl
A comprehensive analysis of the impact of sub 10-nm CNFET technology on 64-bit parallel prefix adders and 32-bit matrix multiply units.
Integr.
Chenlin Shi, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda, Shinobu Miwa
2026 J jnl
Inspex: Speculative Execution of Ready-to-Execute Loads in In-Order Cores.
IEEE Comput. Archit. Lett.
Yotaro Nada, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2025 A conf
AceCov: Auxiliary Composite Edge Coverage for Fuzzing.
EuroS&P
Haruki Yoshida, Yuichi Sugiyama, Ryota Shioya
2025 Misc conf
Analyzing and Mitigating the SSB Vulnerability in an MDP-Equipped RISC-V Processor.
IWSEC
Tuo Chen, Reoma Matsuo, Ryota Shioya, Kuniyasu Suzaki
2025 B conf
Biotite: A High-Performance Static Binary Translator using Source-Level Information.
CC
Changbin Chen, Shu Sugita, Yotaro Nada, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2025 — conf
CACTI-CNFET: an Analytical Tool for Timing, Power, and Area of SRAMs with Carbon Nanotube Field Effect Transistors.
ASP-DAC
Shinobu Miwa, Eiichiro Sekikawa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda
2025 J jnl
Enhancing GPU Performance Through Complexity-Effective Out-of-Order Execution Using Distance-Based ISA.
IEICE Trans. Inf. Syst.
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2025 J jnl
Flexible Approximate Computing for Mitigating Branch Divergence in GPUs.
IEEE Micro
Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2025 — conf
PEZY-SC4s : The Fourth Generation MIMD Many-core Processor with High Energy Efficiency and Flexibility for HPC and AI Applications.
HCS
Naoya Hatta, Shuntaro Tsunoda, Kouhei Uchida, Taichi Ishitani, Toru Koizumi, Ryota Shioya, Kei Ishii
2025 C conf
Register Bridging: A Lightweight Microarchitectural Approach for Skipping Overhead Instructions in Distance-Based ISA Processors.
ICCD
Fan Yang, Toru Koizumi, Jun Li, Shu Sugita, Yuriko Yamauchi, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie
2025 C conf
Trailing-Ones Anticipation for Reducing the Latency of the Rounding Incrementer in FP FMA Units.
ARITH
Toru Koizumi, Ryota Shioya, Takuya Yamauchi, Tomoya Adachi, Ken Namura, Jun Makino
2024 — conf
Branch Divergence-Aware Flexible Approximating Technique on GPUs.
COOL CHIPS
Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2024 J jnl
CNFET-OCL: Open-Source Cell Libraries for Advanced CNFET Technologies.
IEEE Access
Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda
2024 C conf
Dynamic Controllability Analysis for Preventing Injection Attacks.
PRDC
Eri Ogawa, Tetsuro Yamazaki, Ryota Shioya
2024 C conf
Dynamic Possible Source Count Analysis for Data Leakage Prevention.
MPLR
Eri Ogawa, Tetsuro Yamazaki, Ryota Shioya
2024 — conf
Error Distribution Estimation for Fixed-point Arithmetic using Program Derivatives.
ISQED
Soramichi Akiyama, Ryota Shioya, Yuto Miyatake, Tongxin Yang
2024 A conf
ReOVE: Restricted Out-of-Order Execution for Superscalar Processors with Vector Extension.
ISLPED
Masayuki Kimura, Ryota Shioya
2024 J jnl
TURBULENCE: Complexity-Effective Out-of-Order Execution on GPU With Distance-Based ISA.
IEEE Comput. Archit. Lett.
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2024 J jnl
Veryl: A New Hardware Description Language as an Altarnative to SystemVerilog.
CoRR
Naoya Hatta, Taichi Ishitani, Ryota Shioya
2023 J jnl
A Principal Factor of Performance in Decoupled Front-End.
IEICE Trans. Inf. Syst.
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 B conf
A Sound and Complete Algorithm for Code Generation in Distance-Based ISA.
CC
Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2023 C conf
An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS.
ISCAS
Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2023 — conf
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology.
ASP-DAC
Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda
2023 A* conf
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors.
MICRO
Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 J jnl
Collecting Cyclic Garbage across Foreign Function Interfaces: Who Takes the Last Piece of Cake?
Proc. ACM Program. Lang.
Tetsuro Yamazaki, Tomoki Nakamaru, Ryota Shioya, Tomoharu Ugawa, Shigeru Chiba
2023 A conf
Out-of-Step Pipeline for Gather/Scatter Instructions.
DATE
Yi Ge, Katsuhiro Yoda, Makiko Ito, Toshiyuki Ichiba, Takahide Yoshikawa, Ryota Shioya, Masahiro Goshima
2023 J jnl
PEZY-SC3: A MIMD Many-core Processor for Energy-efficient Computing.
CoRR
Naoya Hatta, Shuntaro Tsunoda, Kouhei Uchida, Taichi Ishitani, Ryota Shioya, Kei Ishii
2023 A conf
SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs.
ICCAD
Yuichi Sugiyama, Reoma Matsuo, Ryota Shioya
2023 A conf
TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA.
DATE
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2022 J jnl
Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison.
IEICE Trans. Inf. Syst.
Yasutaka Matsuda, Ryota Shioya, Hideki Ando
2022 A conf
T-SKID: Predicting When to Prefetch Separately from Address Prediction.
DATE
Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2021 C conf
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end.
ICCD
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2021 C conf
Compiling and Optimizing Real-world Programs for STRAIGHT ISA.
ICCD
Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2021 B conf
The Granularity Gap Problem: A Hurdle for Applying Approximate Memory to Complex Data Layout.
ICPE
Soramichi Akiyama, Ryota Shioya
2021 J jnl
The Granularity Gap Problem: A Hurdle for Applying Approximate Memory to Complex Data Layout.
CoRR
Soramichi Akiyama, Ryota Shioya
2020 B conf
A High-Performance Out-of-Order Soft Processor Without Register Renaming.
FPL
Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2020 C conf
Energy Efficient Runahead Execution on a Tightly Coupled Heterogeneous Core.
HPC Asia
Susumu Mashimo, Ryota Shioya, Koji Inoue
2019 — conf
An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor.
FPT
Susumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima
2019 J jnl
Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline.
IEEE Comput. Archit. Lett.
Reoma Matsuo, Ryota Shioya, Hideki Ando
2018 — conf
A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode.
ARCS
Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando
2018 — conf
An Analysis and a Solution of False Conflicts for Hardware Transactional Memory.
ICECS
Yuki Futamase, Masaki Hayashi, Tomoki Tajimi, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura
2018 — conf
An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming.
FPT
Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2018 — conf
Application of Timing Fault Detection to Rocket Core on FPGA.
CANDAR Workshops
Ushio Jimbo, Ryota Shioya, Masahiro Goshima
2018 J jnl
Bank-Aware Instruction Scheduler for a Multibanked Register File.
J. Inf. Process.
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
2018 — conf
Isolation-Safe Speculative Access Control for Hardware Transactional Memory.
ICECS
Tomoki Tajimi, Masaki Hayashi, Yuki Futamase, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura
2018 J jnl
Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications.
J. Inf. Process.
Keita Doi, Ryota Shioya, Hideki Ando
2018 C conf
Rearranging Random Issue Queue with High IPC and Short Delay.
ICCD
Shinji Sakai, Taishi Suenaga, Ryota Shioya, Hideki Ando
2018 A* conf
STRAIGHT: Hazardless Processor Architecture Without Register Renaming.
MICRO
Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai
2018 J jnl
VMOR: Microarchitectural Support for Operand Access in an Interpreter.
IEEE Comput. Archit. Lett.
Susumu Mashimo, Ryota Shioya, Koji Inoue
2017 J jnl
Applying Razor Flip-Flops to SRAM Read Circuits.
IEICE Trans. Electron.
Ushio Jimbo, Junji Yamada, Ryota Shioya, Masahiro Goshima
2017 J jnl
Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology.
IEICE Trans. Electron.
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
2017 — conf
Initial study of a phase-aware scheduling for hardware transactional memory.
PACRIM
Tomoki Tajimi, Anju Hirota, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura
2017 J jnl
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency.
IEICE Trans. Inf. Syst.
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
2016 J jnl
FXA: Executing Instructions in Front-End for Energy Efficiency.
IEICE Trans. Inf. Syst.
Ryota Shioya, Ryo Takami, Masahiro Goshima, Hideki Ando
2016 J jnl
Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency.
IEICE Trans. Inf. Syst.
Ryota Shioya, Hideki Ando
2016 J jnl
Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control.
IEICE Trans. Inf. Syst.
Hideki Ando, Ryota Shioya
2015 J jnl
Address Order Violation Detection with Parallel Counting Bloom Filters.
IEICE Trans. Electron.
Naruki Kurata, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
2014 A* conf
A Front-End Execution Architecture for High Energy Efficiency.
MICRO
Ryota Shioya, Masahiro Goshima, Hideki Ando
2014 C conf
Energy efficiency improvement of renamed trace cache through the reduction of dependent path length.
ICCD
Ryota Shioya, Hideki Ando
2013 J jnl
Register Indirect Jump Target Forwarding.
IEICE Trans. Inf. Syst.
Ryota Shioya, Naruki Kurata, Takashi Toyoshima, Masahiro Goshima, Shuichi Sakai
2011 J jnl
Low-Overhead Architecture for Security Tag.
IEICE Trans. Inf. Syst.
Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
2010 A* conf
Register Cache System Not for Latency Reduction Purpose.
MICRO
Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
2009 C conf
Low-Overhead Architecture for Security Tag.
PRDC
Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
2009 C conf
String-Wise Information Flow Tracking against Script Injection Attacks.
PRDC
Kunbo Li, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
2006 C conf
Base Address Recognition with Data Flow Tracking for Injection Attack Detection.
PRDC
Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai