Ruzica Jevtic

24 papers C 1Journal 13Unranked 10
YearRankTypeTitle / Venue / Authors
2025 J jnl
Side-channel attacks and countermeasures for heart rate retrieval from ECG characterization device.
Int. J. Inf. Sec.
Pablo Pérez-Tirador, Madhav P. Desai, Alejandro Rodriguez, Elena Berral, Teresa Romero, Gabriel Caffarena, Ruzica Jevtic
2025 J jnl
The effect of ECG data variability on side-channel attack success rate in wearable devices.
Integr.
Pablo Pérez-Tirador, Ruzica Jevtic, Carmen Cabezaolias, Teresa Romero, Abraham Otero, Gabriel Caffarena
2022 J jnl
Methodology for Complete Decorrelation of Power Supply EM Side-Channel Signal and Sensitive Data.
IEEE Trans. Circuits Syst. II Express Briefs
Ruzica Jevtic, Mariano García Otero
2022 — conf
Side-channel Attack Countermeasure Based on Power Supply Modulation.
EUSIPCO
Ruzica Jevtic, Pablo Pérez-Tirador, Carmen Cabezaolias, Pablo Carnero, Gabriel Caffarena
2021 J jnl
EM Side-Channel Countermeasure for Switched-Capacitor DC-DC Converters Based on Amplitude Modulation.
IEEE Trans. Very Large Scale Integr. Syst.
Ruzica Jevtic, Marko Ylitolva, Clara Calonge, Martti Ojanen, Tero Säntti, Lauri Koskinen
2018 — conf
Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices.
PATMOS
Ruzica Jevtic, Marko Ylitolva, Lauri Koskinen
2016 J jnl
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.
IEEE J. Solid State Circuits
Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Steven Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic
2016 J jnl
An Agile Approach to Building RISC-V Microprocessors.
IEEE Micro
Yunsup Lee, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Rimas Avizienis, Brian C. Richards, Jonathan Bachrach, David A. Patterson, Elad Alon, Bora Nikolic, Krste Asanovic
2015 C conf
A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator.
ISCAS
Fernando Cardes, Ruzica Jevtic, Luis Hernández, Andreas Wiesbauer, Dietmar Sträußnigg, Richard Gaggl
2015 — conf
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.
VLSIC
Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic
2015 — conf
Fully integrated DC-DC converter and a 0.4V 32-bit CPU with timing-error prevention supplied from a prototype 1.55V Li-ion battery.
VLSIC
Matthew J. Turnquist, Markus Hiienkari, Jani Mäkipää, Ruzica Jevtic, Elina Pohjalainen, Tanja Kallio, Lauri Koskinen
2015 J jnl
Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Ruzica Jevtic, Hanh-Phuc Le, Milovan Blagojevic, Stevo Bailey, Krste Asanovic, Elad Alon, Borivoje Nikolic
2015 — conf
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking.
Hot Chips Symposium
Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian C. Richards, Elad Alon, Borivoje Nikolic, Krste Asanovic
2014 J jnl
Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits.
IEEE Trans. Ind. Informatics
Bojan Jovanovic, Ruzica Jevtic, Carlos Carreras
2014 J jnl
Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes.
J. Syst. Archit.
Pablo Barrio, Carlos Carreras, Juan A. López, Óscar Robles, Ruzica Jevtic, Roberto Sierra
2012 J jnl
A complete dynamic power estimation model for data-paths in FPGA DSP designs.
Integr.
Ruzica Jevtic, Carlos Carreras
2011 J jnl
Power Measurement Methodology for FPGA Devices.
IEEE Trans. Instrum. Meas.
Ruzica Jevtic, Carlos Carreras
2011 — conf
Power estimation of dividers implemented in FPGAs.
ACM Great Lakes Symposium on VLSI
Ruzica Jevtic, Bojan Jovanovic, Carlos Carreras
2011 J jnl
Technology Variability From a Design Perspective.
IEEE Trans. Circuits Syst. I Regul. Pap.
Borivoje Nikolic, Ji-Hoon Park, Jaehwa Kwak, Bastien Giraud, Zheng Guo, Liang-Teck Pang, Seng Oon Toh, Ruzica Jevtic, Kun Qian, Costas J. Spanos
2010 J jnl
Power Estimation of Embedded Multiplier Blocks in FPGAs.
IEEE Trans. Very Large Scale Integr. Syst.
Ruzica Jevtic, Carlos Carreras
2009 — conf
Floorplan-based FPGA interconnect power estimation in DSP circuits.
SLIP
Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic
2008 — conf
A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components.
ReConFig
Ruzica Jevtic, Carlos Carreras, Domenik Helms
2008 — conf
Analytical High-Level Power Model for LUT-Based Components.
PATMOS
Ruzica Jevtic, Carlos Carreras
2007 — conf
Switching Activity Models for Power Estimation in FPGA Multipliers.
ARC
Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena