Russ Joseph - RankMe

36 papers A* 10A 5B 3C 1Misc 3Journal 8Unranked 6

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Saving Energy with Per-Variable Bitwidth Speculation. ASPLOS (2) Tommy McMichen, David Dlott, Panitan Wongse-ammat, Nathan Greiner, Hussain Khajanchi, Russ Joseph, Simone Campanoni
2025	C	`conf`	Supporting Pipelined Memory Accesses in Processor Synthesis. ICCD Essien Taylor, Colin Schilf, Sebastian Phemister, Russ Joseph
2020	J	`jnl`	An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture. IEEE J. Solid State Circuits Tianyu Jia, Yijie Wei, Russ Joseph, Jie Gu
2020	A*	`conf`	NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance. MICRO Tianyu Jia, Yuhao Ju, Russ Joseph, Jie Gu
2019	—	`conf`	An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution. ISSCC Tianyu Jia, Russ Joseph, Jie Gu
2019	J	`jnl`	An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor. IEEE J. Solid State Circuits Tianyu Jia, Russ Joseph, Jie Gu
2019	A*	`conf`	Time squeezing for tiny devices. ISCA Yuanbo Fan, Simone Campanoni, Russ Joseph
2018	—	`conf`	An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. ESSCIRC Tianyu Jia, Russ Joseph, Jie Gu
2018	—	`conf`	Cocoa: synergistic cache compression and error correction in capacity sensitive last level caches. MEMSYS Chao Yan, Russ Joseph
2018	A*	`conf`	Compiler-guided instruction-level clock scheduling for timing speculative processors. DAC Yuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russ Joseph
2017	—	`conf`	(Invited) Software-guided greybox design methodology with integrated power and clock management. MWSCAS Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu
2017	—	`conf`	D2M: data-driven model for fast and accurate timing error simulation in statically scheduled microprocessors. SummerSim Yuanbo Fan, Russ Joseph
2017	A*	`conf`	Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management. DAC Tianyu Jia, Russ Joseph, Jie Gu
2016	A	`conf`	Enabling Deep Voltage Scaling in Delay Sensitive L1 Caches. DSN Chao Yan, Russ Joseph
2016	A*	`conf`	Exploration of associative power management with instruction governed operation for ultra-low power design. DAC Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu
2015	Misc	`conf`	Embedded system and application aware design of deregulated energy delivery systems. CASES Xuejing He, Robert P. Dick, Russ Joseph
2012	J	`jnl`	Reliability Modeling and Management of Nanophotonic On-Chip Networks. IEEE Trans. Very Large Scale Integr. Syst. Zheng Li, Moustafa Mohamed, Xi Chen, Eric Dudley, Ke Meng, Li Shang, Alan Rolf Mickelson, Russ Joseph, Manish Vachharajani, Brian Schwartz, Yihe Sun
2012	Misc	`conf`	Spatially- and temporally-adaptive communication protocols for zero-maintenance sensor networks relying on opportunistic energy scavenging. CODES+ISSS Xuejing He, Robert P. Dick, Russ Joseph
2012	J	`jnl`	Virtual-machine-based emulation of future generation high-performance computing systems. Int. J. High Perform. Comput. Appl. Patrick G. Bridges, Dorian C. Arnold, Kevin T. Pedretti, Madhav Suresh, Feng Lu, Peter A. Dinda, Russ Joseph, Jack Lange
2011	A	`conf`	Efficient parameter variation sampling for architecture simulations. DATE Feng Lu, Russ Joseph, Goce Trajcevski, Song Liu
2011	A*	`conf`	Exploring circuit timing-aware language and compilation. ASPLOS Giang Hoang, Robby Bruce Findler, Russ Joseph
2011	A*	`conf`	Identifying and predicting timing-critical instructions to boost timing speculation. MICRO Jing Xin, Russ Joseph
2010	J	`jnl`	A Case for Alternative Nested Paging Models for Virtualized Systems. IEEE Comput. Archit. Lett. Giang Hoang, Chang Bae, Jack Lange, Lide Zhang, Peter A. Dinda, Russ Joseph
2009	J	`jnl`	Exploiting Locality to Improve Circuit-Level Timing Speculation. IEEE Comput. Archit. Lett. Jing Xin, Russ Joseph
2009	A*	`conf`	Process variation characterization of chip-level multiprocessors. DAC Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph
2008	B	`conf`	Multi-optimization power management for chip multiprocessors. PACT Ke Meng, Russ Joseph, Robert P. Dick, Li Shang
2008	J	`jnl`	Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Russ Joseph
2007	B	`conf`	Modeling and Characterizing Power Variability in Multicore Architectures. ISPASS Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ismail
2007	Misc	`conf`	Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems. CODES+ISSS Seunghoon Kim, Robert P. Dick, Russ Joseph
2007	J	`jnl`	Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors. IEEE Micro David M. Brooks, Robert P. Dick, Russ Joseph, Li Shang
2007	A	`conf`	Understanding voltage variations in chip multiprocessors using a distributed power-delivery network. DATE Meeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, David M. Brooks
2006	A	`conf`	Process variation aware cache leakage management. ISLPED Ke Meng, Russ Joseph
2004	B	`conf`	Spectral analysis for characterizing program power and performance. ISPASS Russ Joseph, Margaret Martonosi, Zhigang Hu
2004	A*	`conf`	Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization. HPCA Russ Joseph, Zhigang Hu, Margaret Martonosi
2003	A*	`conf`	Control Techniques to Eliminate Voltage Emergencies in High Performance Processors. HPCA Russ Joseph, David M. Brooks, Margaret Martonosi
2001	A	`conf`	Run-time power estimation in high performance microprocessors. ISLPED Russ Joseph, Margaret Martonosi