Rupesh S. Shelar

21 papers A 3C 1Journal 7Unranked 8
YearRankTypeTitle / Venue / Authors
2020 A conf
An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops.
FPGA
Rupesh S. Shelar
2013 J jnl
Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rupesh S. Shelar, Marek Patyra
2012 J jnl
A Fast and Near-Optimal Clustering Algorithm for Low-Power Clock Tree Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rupesh S. Shelar
2011 J jnl
Simultaneous Technology Mapping and Placement for Delay Minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yifang Liu, Rupesh S. Shelar, Jiang Hu
2010 — conf
Impact of local interconnects on timing and power in a high performance microprocessor.
ISPD
Rupesh S. Shelar, Marek Patyra
2010 J jnl
Routing With Constraints for Post-Grid Clock Distribution in Microprocessors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rupesh S. Shelar
2009 — conf
An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors.
ISPD
Rupesh S. Shelar
2008 A conf
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization.
ICCAD
Yifang Liu, Rupesh S. Shelar, Jiang Hu
2008 — ch.
Estimation of Routing Congestion.
Handbook of Algorithms for Physical Design Automation
Rupesh S. Shelar, Prashant Saxena
2007 — conf
An efficent clustering algorithm for low power clock tree synthesis.
ISPD
Rupesh S. Shelar
2007 — book
Routing Congestion in VLSI Circuits - Estimation and Optimization.
Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar
2006 J jnl
Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar
2005 J jnl
A predictive distributed congestion metric with application to technology mapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
2005 — conf
An efficient technology mapping algorithm targeting routing congestion under delay constraints.
ISPD
Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar
2005 J jnl
BDD decomposition for delay oriented pass transistor logic synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Rupesh S. Shelar, Sachin S. Sapatnekar
2004 — conf
A predictive distributed congestion metric and its application to technology mapping.
ISPD
Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
2002 — conf
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis.
ASP-DAC/VLSI Design
Rupesh S. Shelar, Sachin S. Sapatnekar
2002 — conf
Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits.
IWLS
Rupesh S. Shelar, Sachin S. Sapatnekar
2001 A conf
Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits.
ICCAD
Rupesh S. Shelar, Sachin S. Sapatnekar
2000 — conf
Parameterized Reusable Component Library Methodology.
EUROMICRO
Rupesh S. Shelar, Sacheendra Nath, Jagmohan S. Nanaware
1999 C conf
Decomposition of Finite State Machines for Area, Delay Minimization.
ICCD
Rupesh S. Shelar, Madhav P. Desai, H. Narayanan