Rung-Bin Lin

74 papers A* 1A 10C 5Misc 2Journal 17Unranked 39
YearRankTypeTitle / Venue / Authors
2025 C conf
A 4.5-Track Standard Cell Library with Buried Power Rails in 7nm Node.
ISCAS
Kai-Jie Tong, Ting-An Jian, Shang-Mou Zhou, Yi-Jia Wu, Bo-Xiang Yang, Meng-Ru Lin, Ming-Yi Huang, Shi-Xian Tang, Ya-Zhu Yang, Zheng-Jie Peng, Yu-Cheng Lin, Rung-Bin Lin
2025 J jnl
A Multi-stage Error Diagnosis for APB Transaction.
CoRR
Cheng-Yang Tsai, Tzu-Wei Huang, Jen-Wei Shih, I-Hsiang Wang, Yu-Cheng Lin, Rung-Bin Lin
2025 J jnl
Subitizing-Inspired_Large_Language_Models_for_Floorplanning.
CoRR
Shao-Chien Lu, Chen-Chen Yeh, Hui-Lin Cho, Yu-Cheng Lin, Rung-Bin Lin
2024 — conf
Engineering ASAP7 PDK with Buried Power Rail and Backside Metal Technologies.
APCCAS
Wen-cheng Yang, Ting-An Jian, Yu-Cheng Lin, Rung-Bin Lin
2024 — conf
Routing Intent Aware Pin Access Point Selection for Standard Cell Designs.
ISQED
Po-Chun Wang, Kai-Jie Ton, Rung-Bin Lin
2024 — conf
Standard Cells with Inverted Inputs in 7nm Technology.
APCCAS
Tung-Chun Wu, Rung-Bin Lin
2024 C conf
Sub-10nm Standard Cell Library Design Methodology for On-Grid Pin Accesses.
ISCAS
Rung-Bin Lin, Pei-Sheng Lu
2023 — conf
Improving Pin Accessibility of Standard Cells under Power/Ground Stripes.
NEWCAS
Pei-Sheng Lu, Rung-Bin Lin
2022 — conf
Improving Pin Accessibility of Standard Cell Libraries in 7nm Technology.
ISQED
Tsao-Hsuan Peng, Chih-Chun Hsu, Po-Chun Wang, Rung-Bin Lin
2021 — conf
Six-track Standard Cell Libraries with Fin Depopulation, Contact over Active Gate, and Narrower Diffusion Break in 7nm Technology.
ISQED
Tzu-Hsuan Wang, Chih-Chun Hsu, Li Kao, Bing-Yu Li, Tung-Chun Wu, Tsao-Hsuan Peng, Rung-Bin Lin
2020 — conf
Engineering a Standard Cell Library for an Industrial Router with ASAP7 PDK.
ISVLSI
Yuan-Dar Chung, Rung-Bin Lin
2019 — conf
Impact of Double-Row Height Standard Cells on Placement and Routing.
ISQED
Rung-Bin Lin, Yu-Xiang Chiang
2019 — conf
Morphed Standard Cell Layouts for Pin Length Reduction.
ISVLSI
Cheng-Wei Tai, Rung-Bin Lin
2018 J jnl
A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction.
ACM Trans. Design Autom. Electr. Syst.
Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin
2018 — conf
Designing and Benchmarking of Double-Row Height Standard Cells.
ISVLSI
Yu-Xiang Chiang, Cheng-Wei Tai, Shang-Rong Fang, Kai-Chun Peng, Yuan-Dar Chung, Jin-Kai Yang, Rung-Bin Lin
2018 — conf
Recognition of regular layout structures.
ISQED
Yu-Cheng Chiang, Shr-Cheng Tsai, Rung-Bin Lin
2017 — conf
A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points.
ACM Great Lakes Symposium on VLSI
Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin
2017 — conf
On Benchmarking Pin Access for Nanotechnology Standard Cells.
ISVLSI
Shang-Rong Fang, Cheng-Wei Tai, Rung-Bin Lin
2017 A conf
Overview of the 2017 CAD contest at ICCAD: Invited paper.
ICCAD
Myung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake
2016 — conf
Design Space Exploration of FinFETs with Double Fin Heights for Standard Cell Library.
ISVLSI
Chi-Hung Lin, Chia-Shiang Chen, Yu-He Chang, Yu Ting Zhang, Shang-Rong Fang, Santanu Santra, Rung-Bin Lin
2016 — conf
Multiple-patterning lithography-aware routing for standard cell layout synthesis.
APCCAS
Kuen-Wey Lin, Yih-Lang Li, Rung-Bin Lin
2016 A conf
Overview of the 2016 CAD contest at ICCAD.
ICCAD
Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake
2016 A conf
Practical ILP-based routing of standard cells.
DATE
Hsueh-Ju Lu, En-Jang Jang, Ang Lu, Yu Ting Zhang, Yu-He Chang, Chi-Hung Lin, Rung-Bin Lin
2015 — conf
A router for via configurable structured ASIC with standard cells and relocatable IPs.
ISQED
Chiung-Chih Ho, Hsin-Pei Tsai, Liang-Chi Lai, Rung-Bin Lin
2015 A conf
Overview of the 2015 CAD Contest at ICCAD.
ICCAD
Natarajan Viswanathan, Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim
2015 A conf
Simultaneous transistor pairing and placement for CMOS standard cells.
DATE
Ang Lu, Hsueh-Ju Lu, En-Jang Jang, Yu-Po Lin, Chun-Hsiang Hung, Chun-Chih Chuang, Rung-Bin Lin
2014 — conf
Logic block and design methodology for via-configurable structured ASIC using dual supply voltages.
ACM Great Lakes Symposium on VLSI
Ta-Kai Lin, Kuen-Wey Lin, Chang-Hao Chiu, Rung-Bin Lin
2014 — conf
Transition inversion coding with parity check for off-chip serial transmission.
ICECS
Jian Zeng, Jian-Yang Zhou, Rung-Bin Lin
2013 — conf
Relocatable and resizable SRAM synthesis for via configurable structured ASIC.
ISQED
Hsin-Hung Liu, Rung-Bin Lin, I-Lun Tseng
2013 A conf
Slack budgeting and slack to length converting for multi-bit flip-flop merging.
DATE
Chia-Chieh Lu, Rung-Bin Lin
2012 J jnl
$2^{n}$ Pattern Run-Length for Test Data Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Cheng-Ho Chang
2012 A conf
Design and analysis of via-configurable routing fabrics for structured ASICs.
DATE
Hsin-Pei Tsai, Rung-Bin Lin, Liang-Chi Lai
2012 J jnl
Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow.
IEEE Trans. Very Large Scale Integr. Syst.
Hui-Hsiang Tung, Rung-Bin Lin, Mei-Chen Li, Tsung-Han Heish
2011 A conf
Clock gating optimization with delay-matching.
DATE
Shih-Jung Hsu, Rung-Bin Lin
2011 — conf
Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs.
ACM Great Lakes Symposium on VLSI
Liang-Chi Lai, Hsih-Hang Chang, Rung-Bin Lin
2010 — conf
Clock routing for structured ASICs with via-configurable fabrics.
ISQED
Rung-Bin Lin, I-Wei Lee, Wen-Hao Chen
2010 J jnl
Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction.
IET Comput. Digit. Tech.
Wang-Dauh Tseng, Lung-Jen Lee, Rung-Bin Lin
2010 A conf
Power gating design for standard-cell-like structured ASICs.
DATE
Sin-Yu Chen, Rung-Bin Lin, Hui-Hsiang Tung, Kuen-Wey Lin
2010 — conf
Via configurable three-input lookup-tables for structured ASICs.
ACM Great Lakes Symposium on VLSI
Yu-Chen Chen, Hou-Yu Pang, Kuen-Wey Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su
2009 — conf
A Multi-dimensional Pattern Run-Length Method for Test Data Compression.
Asian Test Symposium
Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chen-Lun Lee
2009 — conf
Context-aware Post Routing Redundant Via Insertion.
ISVLSI
Po-Heng Chu, Rung-Bin Lin, Da-Wei Hsu, Yu-Hsing Chen, Wei-Chiu Tseng
2009 — conf
Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing.
Asian Test Symposium
Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chi-Wei Yu
2008 J jnl
Chip placement in a reticle for multiple-project wafer fabrication.
ACM Trans. Design Autom. Electr. Syst.
Meng-Chiou Wu, Rung-Bin Lin, Shih-Cheng Tsai
2008 J jnl
Finding Dicing Plans for Multiple Project wafers fabricated with Shuttle Mask.
J. Circuits Syst. Comput.
Meng-Chiou Wu, Rung-Bin Lin
2008 J jnl
Inter-Wire Coupling Reduction Analysis of Bus-Invert Coding.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rung-Bin Lin
2008 J jnl
Power Reduction during Scan Testing Based on Multiple Capture Technique.
IEICE Trans. Electron.
Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin
2008 C conf
Router and cell library co-development for improving redundant via insertion at pins.
ICCD
Wei-Chiu Tseng, Yu-Hsing Chen, Rung-Bin Lin
2008 — conf
Standard Cell Like Via-Configurable Logic Block for Structured ASICs.
ISVLSI
Mei-Chen Li, Hui-Hsiang Tung, Chien-chung Lai, Rung-Bin Lin
2008 J jnl
Variable-sized object packing and its applications to instruction cache design.
Comput. Electr. Eng.
Rung-Bin Lin
2007 J jnl
Conjugate conflict continuation graphs for multi-layer constrained via minimization.
Inf. Sci.
Rung-Bin Lin, Shuyu Chen
2007 A conf
Double-via-driven standard cell library design.
DATE
Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin
2007 J jnl
Reticle Design for Minimizing Multiproject Wafer Production Cost.
IEEE Trans Autom. Sci. Eng.
Rung-Bin Lin, Meng-Chiou Wu, Shih-Cheng Tsai
2007 C conf
Reticle Exposure Plans for Multi-Project Wafers.
DDECS
Rung-Bin Lin, Da-Wei Hsu, Ming-Hsine Kuo, Meng-Chiou Wu
2006 — conf
Design space exploration for minimizing multi-project wafer production cost.
ASP-DAC
Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai
2006 C conf
Is more redundancy better for on-chip bus encoding.
ISCAS
Hsun-Chieh Yu, Rung-Bin Lin
2005 — conf
A Comparative Study on Dicing of Multiple Project Wafers.
ISVLSI
Meng-Chiou Wu, Rung-Bin Lin
2005 — conf
A divide-and-conquer approach to estimating minimum/maximum leakage current.
ISCAS (5)
Guang-Wan Liao, Ja-Shong Feng, Rung-Bin Lin
2005 — conf
Coupling reduction analysis of bus-invert coding.
ISCAS (6)
Rung-Bin Lin
2005 — conf
Multiple project wafers for medium-volume IC production.
ISCAS (5)
Meng-Chiou Wu, Rung-Bin Lin
2005 — conf
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers.
ISQED
Meng-Chiou Wu, Rung-Bin Lin
2005 — conf
Reticle floorplanning of flexible chips for multi-project wafers.
ACM Great Lakes Symposium on VLSI
Meng-Chiou Wu, Rung-Bin Lin
2004 — conf
Multi-layer constrained via minimization with conjugate conflict continuation graphs.
ISCAS (4)
Rung-Bin Lin, Shuyu Chen
2003 Misc conf
A Low Power-Delay Product Page-Based Address Bus Coding Method.
VLSI Design
Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin
2002 — conf
An Adaptive Interconnect-Length Driven Placer.
ASP-DAC/VLSI Design
Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin
2002 J jnl
Comments on "Filling algorithms and analyses for layout density control".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rung-Bin Lin
2002 J jnl
Theoretical analysis of bus-invert coding.
IEEE Trans. Very Large Scale Integr. Syst.
Rung-Bin Lin, Chi-Ming Tsai
2002 — conf
Weight-Based Bus-Invert Coding for Low-Power Applications.
ASP-DAC/VLSI Design
Rung-Bin Lin, Chi-Ming Tsai
1999 — conf
Benchmark Circuits Improve the Quality of a Standard Cell Library.
ASP-DAC
Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai
1999 — conf
Low Power CMOS Off-Chip Drivers with Slew-rate Difference.
ASP-DAC
Rung-Bin Lin, Jinq-Chang Chen
1998 Misc conf
A New Statistical Approach to Timing Analysis of VLSI Circuits.
VLSI Design
Rung-Bin Lin, Meng-Chiou Wu
1994 J jnl
Fuzzy logic approach to VLSI placement.
IEEE Trans. Very Large Scale Integr. Syst.
Eric Q. Kang, Rung-Bin Lin, Eugene Shragowitz
1993 J jnl
An adaptive timing-driven placement for high performance VLSIs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Suphachai Sutanthavibul, Eugene Shragowitz, Rung-Bin Lin
1992 A* conf
Fuzzy Logic Approach to Placement Problem.
DAC
Rung-Bin Lin, Eugene Shragowitz
1991 — conf
Bounds on Net Delays for Physical Design of Fast Circuits.
VLSI
Habib Youssef, Rung-Bin Lin, Eugene Shragowitz