Ruijun Ma

15 papers B 3Journal 11Unranked 1
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faults.
CoRR
Shaoqi Wei, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Ruijun Ma, Tianming Ni, Xiaoqing Wen, Hiroshi Takahashi
2025 J jnl
ESegNet-ILT: An end-to-end mask optimization method in VLSI design flow based on enhanced SegNet.
Integr.
Hui Xu, Yong Xue, Yu Zhang, Xia Sun, Jiale Li, Ruijun Ma, Huaguo Liang, Zhengfeng Huang
2025 J jnl
Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design.
IEEE Trans. Very Large Scale Integr. Syst.
Ruijun Ma, Stefan Holst, Hui Xu, Xiaoqing Wen, Senling Wang, Jiuqi Li, Aibin Yan
2025 J jnl
Semi-supervised lithography hotspot detection based on feature fusion and residual attention.
Integr.
Hui Xu, Xinzhong Xiao, Wenxin Huang, Ruijun Ma, Fuxin Tang, Pan Qi, Ye Yuan, Huaguo Liang
2024 J jnl
A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches.
J. Electron. Test.
Hui Xu, Xuewei Qin, Ruijun Ma, Chaoming Liu, Shuo Zhu, Jun Wang, Huaguo Liang
2024 J jnl
A Low-Cost Triple-Node-Upset Self-Recovery Latch Design.
J. Circuits Syst. Comput.
Hui Xu, Yu Xia, Ruijun Ma, Huaguo Liang, Zhenfeng Huang
2024 J jnl
A cost-effective and highly robust triple-node-upset self-recoverable latch design based on dual-output C-elements.
Microelectron. J.
Hui Xu, Lin Tang, Ruijun Ma, Huaguo Liang, Zhengfeng Huang, Tianming Ni, Jiuqi Li, Xiaodong Ai
2024 J jnl
Design of novel low cost triple-node-upset self-recoverable hardened latch.
Integr.
Hui Xu, Shuo Zhu, Ruijun Ma, Zhengfeng Huang, Huaguo Liang, Haojie Sun, Chaoming Liu
2024 J jnl
Hardened latch designs based on the characteristic of transistor for mitigating multiple-node-upsets in harsh radiation environments.
Microelectron. J.
Hui Xu, Chaoming Liu, Ruijun Ma, Tai Song, Zhengfeng Huang, Jun Wang, Xuewei Qin, Yu Xia
2024 — conf
Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs.
ITC-Asia
Senling Wang, Shaoqi Wei, Hisashi Okamoto, Tatusya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Ruijun Ma, Tianming Ni, Hiroshi Takahashi, Xiaoqing Wen
2023 B conf
BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell.
ETS
Stefan Holst, Ruijun Ma, Xiaoqing Wen, Aibin Yan, Hui Xu
2023 J jnl
LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy.
Integr.
Hui Xu, Jing Zhou, Ruijun Ma, Huaguo Liang, Zhengfeng Huang, Chaoming Liu
2022 J jnl
Evaluation and Test of Production Defects in Hardened Latches.
IEICE Trans. Inf. Syst.
Ruijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan, Hui Xu
2019 B conf
STAHL: A Novel Scan-Test-Aware Hardened Latch Design.
ETS
Ruijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan, Hui Xu
2018 B conf
The impact of production defects on the soft-error tolerance of hardened latches.
ETS
Stefan Holst, Ruijun Ma, Xiaoqing Wen