Rui Liu

22 papers A* 1A 1C 3Journal 7Unranked 10
YearRankTypeTitle / Venue / Authors
2020 — conf
8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator.
MWSCAS
Hongwu Jiang, Rui Liu, Shimeng Yu
2020 J jnl
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits
Xin Si, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun
2020 J jnl
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Xiaochen Peng, Rui Liu, Shimeng Yu
2019 J jnl
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin Si, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li, Meng-Fan Chang
2019 — conf
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.
ISSCC
Xin Si, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang
2019 — conf
Evaluation of Single Event Effects in SRAM and RRAM Based Neuromorphic Computing System for Inference.
IRPS
Zhilu Ye, Rui Liu, Hugh J. Barnaby, Shimeng Yu
2019 J jnl
Harnessing Intrinsic Noise in Memristor Hopfield Neural Networks for Combinatorial Optimization.
CoRR
Fuxi Cai, Suhas Kumar, Thomas Van Vaerenbergh, Rui Liu, Can Li, Shimeng Yu, Qiangfei Xia, J. Joshua Yang, Raymond G. Beausoleil, Wei Lu, John Paul Strachan
2019 J jnl
MAX
IEEE J. Emerg. Sel. Topics Circuits Syst.
Manqing Mao, Xiaochen Peng, Rui Liu, Jingtao Li, Shimeng Yu, Chaitali Chakrabarti
2019 C conf
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture.
ISCAS
Xiaochen Peng, Rui Liu, Shimeng Yu
2018 — conf
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.
ISSCC
Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang
2018 — conf
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons.
ASP-DAC
Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu
2018 A* conf
Parallelizing SRAM arrays with customized bit-cell for binary neural networks.
DAC
Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu
2018 J jnl
X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rui Liu, Pai-Yu Chen, Xiaochen Peng, Shimeng Yu
2018 A conf
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks.
DATE
Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu
2017 — conf
Analyzing inference robustness of RRAM synaptic array in low-precision neural network.
ESSDERC
Rui Liu, Heng-Yuan Lee, Shimeng Yu
2017 C conf
Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array.
ISCAS
Rui Liu, Pai-Yu Chen, Shimeng Yu
2017 — conf
Extending 1kb RRAM array from weak PUF to strong PUF by employment of SHA module.
AsianHOST
Rui Liu, Huaqiang Wu, Yachun Pang, He Qian, Shimeng Yu
2017 J jnl
Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network.
IEEE Trans. Very Large Scale Integr. Syst.
Xiaoyu Sun, Rui Liu, Yi-Ju Chen, Hsiao-Yun Chiu, Wei-Hao Chen, Meng-Fan Chang, Shimeng Yu
2016 — conf
A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation.
HOST
Rui Liu, Huaqiang Wu, Yachun Pang, He Qian, Shimeng Yu
2016 — conf
Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM.
ACM Great Lakes Symposium on VLSI
Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, Swarup Bhunia
2015 — conf
Exploiting resistive cross-point array for compact design of physical unclonable function.
HOST
Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, Shimeng Yu
2015 C conf
Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design.
ISCAS
Scott Zuloaga, Rui Liu, Pai-Yu Chen, Shimeng Yu