Rubin A. Parekhji

75 papers A* 3A 17B 2C 4Misc 24Journal 11Unranked 14

Year	Rank	Type	Title / Venue / Authors
2025	Misc	`conf`	Defect Severity Analysis for Analog Circuits Using Zoom Search and Hierarchical Fault Simulation. VTS Mehmet Onder, Lakshmanan Balasubramanian, Rubin A. Parekhji, Suriyaprakash Natarajan, Sule Ozev
2025	—	`conf`	Enhancing AMS Circuit Reliability: An Anomaly Dataset for Functional Safety Research in Automotive SoCs. ACM Great Lakes Symposium on VLSI Sanjay Das, Anand Menon, Omar Abiola Abioye, Afreen Fatimah Khazi-Syed, Jonathan Edward Lee, Ayush Arunachalam, Shamik Kundu, Pooja Madhusoodhanan, Prasanth Viswanathan Pillai, Rubin A. Parekhji, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu
2025	A*	`conf`	Machine Learning-Driven STL Generation for Enhancing Functional Safety of E/E Systems. DAC Sanjay Das, Swastik Bhattacharya, Anand Menon, Shamik Kundu, Pooja Madhusoodhanan, Prasanth Viswanathan Pillai, Rubin A. Parekhji, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu
2025	A	`conf`	NeuralTPG: GPU-Accelerated Neural Twin-Based Test Pattern Generation for Transition Delay Faults in Safety-Critical Applications. ITC Xuanyi Tan, Gitanjali Mukherjee, Dhruv Thapar, Arjun Chaudhuri, Sanmitra Banerjee, Rubin A. Parekhji, Krishnendu Chakrabarty
2024	J	`jnl`	Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning. CoRR Ayush Arunachalam, Ian Kintz, Suvadeep Banerjee, Arnab Raha, Xiankun Jin, Fei Su, Viswanathan Pillai Prasanth, Rubin A. Parekhji, Suriyaprakash Natarajan, Kanad Basu
2024	A*	`conf`	Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems. DAC Sanjay Das, Shamik Kundu, Pooja Madhusoodhanan, Viswanathan Pillai Prasanth, Rubin A. Parekhji, Arnab Raha, Suvadeep Banerjee, Suriya Natarajan, Kanad Basu
2024	B	`conf`	Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response Modeling. ETS Tolga Aksoy, Nikhil Sagar Modala, Lakshmanan Balasubramanian, Rubin A. Parekhji, Sule Ozev
2024	—	`conf`	Increasing the Efficiency of Hierarchical Fault Simulation through Functional Fault Clustering. MWSCAS Nikhil Sagar Modala, Lakshmanan Balasubramanian, Rubin A. Parekhji, Sule Ozev
2024	A	`conf`	Safety-Guided Test Generation for Structural Faults. ITC Xuanyi Tan, Dhruv Thapar, Deepesh Sahoo, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty, Rubin A. Parekhji
2022	Misc	`conf`	Innovative Practices Track: New Methods for System Level Test of Image Projection and Radar VLSI Systems. VTS Rubin A. Parekhji
2021	A	`conf`	Exploiting Application Tolerance for Functional Safety. ITC V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur
2019	J	`jnl`	Guest Editorial. J. Electron. Test. Kanad Basu, Mingsong Chen, Rubin A. Parekhji
2019	Misc	`conf`	Perturbation Based Workload Augmentation for Comprehensive Functional Safety Analysis. VLSID V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur
2018	Misc	`conf`	Towards Single Pin Scan for Extremely Low Pin Count Test. VLSID Mudasir S. Kawoosa, Rajesh K. Mittal, Maheedhar Jalasuthram, Rubin A. Parekhji
2017	Misc	`conf`	An optimised SDD ATPG and SDQL computation method across different pattern sets. VTS Wilson Pradeep, Prakash Narayanan, Rubin A. Parekhji
2017	Misc	`conf`	Innovative practices session 2C: "How is industry simplifying analog test". VTS Rubin A. Parekhji, Srinivas Modekurty
2017	A	`conf`	Low cost dynamic error detection in linearity testing of SAR ADCs. ITC Nimit Jain, Nitin Agarwal, Rajavelu Thinakaran, Rubin A. Parekhji
2017	A	`conf`	Safety analysis for integrated circuits in the context of hybrid systems. ITC V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur
2016	Misc	`conf`	A novel technique for interdependent trim code optimization. VTS Pankaj Bongale, Vinothkumar Sundaresan, Partha Ghosh, Rubin A. Parekhji
2015	J	`jnl`	Guest Editors' Introduction: Speeding Up Analog Integration and Test for Mixed-Signal SoCs. IEEE Des. Test Rubin A. Parekhji, Kenneth Butler, Gordon W. Roberts
2015	—	`conf`	Improved Methods for Accurate Safety Analysis of Real-Life Systems. ATS V. Prasanth, Rubin A. Parekhji, Bharadwaj S. Amrutur
2015	Misc	`conf`	New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation. VLSID V. R. Devanathan, Lakshmanan Balasubramanian, Rubin A. Parekhji
2015	A	`conf`	On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADC. DATE Osman Emir Erol, Sule Ozev, Chandra K. H. Suresh, Rubin A. Parekhji, Lakshmanan Balasubramanian
2015	J	`jnl`	Time-Division Multiplexing for Testing DVFS-Based SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji
2014	A	`conf`	Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing. DATE Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain
2014	A	`conf`	Systematic approach for trim test time optimization: Case study on a multi-core RF SOC. ITC Rajesh Mittal, Mudasir Kawoosa, Rubin A. Parekhji
2013	A	`conf`	Towards adaptive test of multi-core RF SoCs. DATE Rajesh Mittal, Lakshmanan Balasubramanian, Y. B. Chethan Kumar, V. R. Devanathan, Mudasir Kawoosa, Rubin A. Parekhji
2012	Misc	`conf`	Derating based hardware optimizations in soft error tolerant designs. VTS V. Prasanth, Virendra Singh, Rubin A. Parekhji
2012	J	`jnl`	Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji
2012	B	`conf`	Time-division multiplexing for testing SoCs with DVS and multiple voltage islands. ETS Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji
2011	Misc	`conf`	An efficient test data reduction technique through dynamic pattern mixing across multiple fault models. VTS Srinivasulu Alampally, R. T. Venkatesh, Priyadharshini Shanmugasundaram, Rubin A. Parekhji, Vishwani D. Agrawal
2011	A	`conf`	DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management. ITC Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji
2011	J	`jnl`	Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test. J. Low Power Electron. Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi
2011	Misc	`conf`	Multi-CoDec Configurations for Low Power and High Quality Scan Test. VLSI Design Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi
2011	C	`conf`	Reduced overhead soft error mitigation using error control coding techniques. IOLTS V. Prasanth, Virendra Singh, Rubin A. Parekhji
2011	—	`conf`	Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands. Asian Test Symposium Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji
2010	Misc	`conf`	A generic low power scan chain wrapper for designs using scan compression. VTS Amit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi, Rubin A. Parekhji
2010	J	`jnl`	False Error Vulnerability Study of On-line Soft Error Detection Mechanisms. J. Electron. Test. M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji
2010	Misc	`conf`	Innovative practices session 1C: Innovative practices in RF test. VTS Rubin A. Parekhji
2010	C	`conf`	Robust detection of soft errors using delayed capture methodology. IOLTS V. Prasanth, Virendra Singh, Rubin A. Parekhji
2010	Misc	`conf`	Test time reduction using parallel RF test techniques. VTS Rajesh Mittal, Adesh Sontakke, Rubin A. Parekhji
2009	—	`conf`	Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage. Asian Test Symposium Hongxia Fang, Krishnendu Chakrabarty, Rubin A. Parekhji
2009	C	`conf`	Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test. IOLTS Amit Dutta, Malav Shah, G. Swathi, Rubin A. Parekhji
2008	Misc	`conf`	A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. VTS Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin A. Parekhji
2008	—	`conf`	A systematic approach to synthesis of verification test-suites for modular SoC designs. SoCC Sudhakar Surendran, Rubin A. Parekhji, R. Govindarajan
2008	A	`conf`	DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs. ITC Amit Dutta, Srinivasulu Alampally, V. Prasanth, Rubin A. Parekhji
2008	—	`conf`	Evaluation of Entropy Driven Compression Bounds on Industrial Designs. ATS Srinivasulu Alampally, Jais Abraham, Rubin A. Parekhji, Rohit Kapur, Thomas W. Williams
2008	C	`conf`	False Error Study of On-line Soft Error Detection Mechanisms. IOLTS M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji
2008	J	`jnl`	Low Power Test for Nanometer System-on-Chips (SoCs). J. Low Power Electron. Srivaths Ravi, Rubin A. Parekhji, Jayashree Saxena
2008	—	`conf`	Power Analysis and Reduction Techniques for Transition Fault Testing. ATS Khushboo Agarwal, Srinivas Vooka, Srivaths Ravi, Rubin A. Parekhji, Arjun Singh Gill
2007	Misc	`conf`	Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs. VLSI Design Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji
2007	A	`conf`	Methodology for low power test pattern generation using activity threshold control logic. ICCAD Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji
2007	Misc	`conf`	Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs. VLSI Design Subir K. Roy, Rubin A. Parekhji
2007	Misc	`conf`	Modified Stability Checking for On-line Error Detection. VLSI Design Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji
2006	A	`conf`	On-chip Test and Repair of Memories for Static and Dynamic Faults. ITC Sanjay K. Thakur, Rubin A. Parekhji, Arun N. Chandorkar
2006	Misc	`conf`	Session Abstract. VTS Rubin A. Parekhji
2005	—	`conf`	Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency. Asian Test Symposium Sameer Goel, Rubin A. Parekhji
2005	—	`conf`	DFT for Low Cost SOC Test. Asian Test Symposium Rubin A. Parekhji
2004	Misc	`conf`	Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories. VLSI Design Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar
2004	—	`conf`	CESC: a visual formalism for specification and verification of SoCs. ACM Great Lakes Symposium on VLSI Ambar A. Gadkari, S. Ramesh, Rubin A. Parekhji
2004	A	`conf`	DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device. ITC K. Nikila, Rubin A. Parekhji
2004	J	`jnl`	ITC 2003 panels: Part 1. IEEE Des. Test Comput. Carol Stolicny, Tapio Koivukangas, Rubin A. Parekhji, Ian G. Harris, Rob Aitken
2003	A	`conf`	Panel Synopsis - How (In)Adequate is One Time Testing? ITC Rubin A. Parekhji
2003	Misc	`conf`	Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions. VLSI Design Rubin A. Parekhji
2002	—	`conf`	Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. ASP-DAC/VLSI Design Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji
2000	A	`conf`	A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx. ITC Jais Abraham, Narayan Prasad, Srinivasa Chakravarthy B. S., Ameet Bagwe, Rubin A. Parekhji
2000	—	`conf`	Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems. Asian Test Symposium Ameet Bagwe, Rubin A. Parekhji
2000	Misc	`conf`	Test Techniques and Trade-offs for Embedded Cores and Systems. VLSI Design Rubin A. Parekhji
1996	—	`conf`	E-Groups: A New Technique for Fast Backward Propagation in System Level Test Generation. Asian Test Symposium Michael Nicolaidis, Rubin A. Parekhji, M. Boudjit
1996	J	`jnl`	Monitoring machine based synthesis technique for concurrent error detection in finite state machines. J. Electron. Test. Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
1995	Misc	`conf`	A new methodology for the design of low-cost fail safe circuits and networks. VLSI Design B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh
1995	J	`jnl`	Concurrent Error Detection Using Monitoring Machines. IEEE Des. Test Comput. Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
1993	Misc	`conf`	State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. VLSI Design Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
1991	A	`conf`	A Methodology for Designing Optimal Self-Checking Sequential Circuits. ITC Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
1989	A*	`conf`	Design methodology and microdiagnostics development for a self-checking microprocessor. MICRO Rubin A. Parekhji, N. K. Nanda