Ruben Gran Tejero

28 papers A 2C 4Misc 2Journal 16Unranked 4
YearRankTypeTitle / Venue / Authors
2024 C conf
Ensuring the Accuracy of CNN Accelerators Supplied at Ultra-Low Voltage.
ICCD
Yamilka Toca-Díaz, Ruben Gran Tejero, Alejandro Valero
2024 J jnl
Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage.
Microprocess. Microsystems
Yamilka Toca-Díaz, Reynier Hernández Palacios, Ruben Gran Tejero, Alejandro Valero
2024 J jnl
Shift-and-Safe: Addressing permanent faults in aggressively undervolted CNN accelerators.
J. Syst. Archit.
Yamilka Toca-Díaz, Ruben Gran Tejero, Alejandro Valero
2023 C conf
On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators.
DSD
Yamilka Toca-Díaz, Nicolás Landeros Muñoz, Ruben Gran Tejero, Alejandro Valero
2022 J jnl
A cross-platform OpenVX library for FPGA accelerators.
J. Syst. Archit.
Maria Angélica Dávila-Guzmán, Lester Kalms, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia, Diana Göhringer
2022 J jnl
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators.
J. Syst. Archit.
Nicolás Landeros Muñoz, Alejandro Valero, Ruben Gran Tejero, Davide Zoni
2022 — conf
peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter.
DCIS
Darío Suárez Gracia, Alejandro Valero, Ruben Gran Tejero, María Villarroya-Gaudó, Víctor Viñals
2021 C conf
A Cross-Platform OpenVX Library for FPGA Accelerators.
PDP
Maria Angélica Dávila-Guzmán, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia, Lester Kalms, Diana Göhringer
2021 J jnl
A generic framework to integrate data caches in the WCET analysis of real-time systems.
J. Syst. Archit.
Juan Segarra, Ruben Gran Tejero, Víctor Viñals
2021 J jnl
A learning experience toward the understanding of abstraction-level interactions in parallel applications.
J. Parallel Distributed Comput.
Alejandro Valero, Ruben Gran Tejero, Darío Suárez Gracia, Emanuel A. Georgescu, Joaquín Ezpeleta, Pedro Álvarez, Adolfo Muñoz, Luis M. Ramos, Pablo Ibáñez
2021 J jnl
Analytical Model for Memory-Centric High Level Synthesis-Generated Applications.
IEEE Trans. Computers
Maria Angélica Dávila-Guzmán, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia
2021 J jnl
RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU.
CoRR
Yamilka Toca-Díaz, Alejandro Valero, Ruben Gran Tejero, Darío Suárez Gracia
2020 Misc conf
An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis.
FCCM
Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia
2020 J jnl
Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis.
CoRR
Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia
2020 J jnl
Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches.
IEEE Access
Juan Segarra, Jordi Cortadella, Ruben Gran Tejero, Víctor Viñals Yúfera
2020 J jnl
DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files.
IEEE Access
Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero
2019 J jnl
Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL.
J. Supercomput.
Maria Angelica Davila Guzman, Raúl Nozal, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia, José Luis Bosque
2019 J jnl
Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs.
J. Syst. Archit.
Andrés Rodríguez, Angeles G. Navarro, Rafael Asenjo, Francisco Corbera, Ruben Gran Tejero, Darío Suárez Gracia, José L. Núñez-Yáñez
2019 — conf
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer.
WCAE@ISCA
Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez, Víctor Viñals
2018 J jnl
Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems.
CoRR
José L. Núñez-Yáñez, Mohammad Hosseinabady, Moslem Amiri, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia
2018 — conf
Towards the Inclusion of FPGAs on Commodity Heterogeneous Systems.
HPCS
Maria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia
2017 — conf
Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip.
PARCO
José L. Núñez-Yáñez, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia
2015 Misc conf
Adaptive Partitioning for Irregular Applications on Heterogeneous CPU-GPU Chips.
ICCS
Antonio Vilches, Rafael Asenjo, Angeles G. Navarro, Francisco Corbera, Ruben Gran Tejero, María Jesús Garzarán
2013 J jnl
Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems.
J. Syst. Archit.
Ruben Gran Tejero, Juan Segarra, Clemente Rodríguez, Luis C. Aparicio, Víctor Viñals
2012 A conf
A Small and Effective Data Cache for Real-Time Multitasking Systems.
IEEE Real-Time and Embedded Technology and Applications Symposium
Juan Segarra, Clemente Rodríguez, Ruben Gran Tejero, Luis C. Aparicio, Víctor Viñals
2012 J jnl
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache.
ACM Trans. Archit. Code Optim.
Jorge Albericio, Ruben Gran Tejero, Pablo Ibáñez, Víctor Viñals, José María Llabería
2009 A conf
On reducing misspeculations in a pipelined scheduler.
IPDPS
Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería
2006 C conf
An Enhancement for a Scheduling Logic Pipelined over two Cycles .
ICCD
Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería