Roy Paily

23 papers A 1C 3Misc 4Journal 12Unranked 3
YearRankTypeTitle / Venue / Authors
2022 J jnl
Design and Implementation of Adaptive Binary Divider for Fixed-Point and Floating-Point Numbers.
Circuits Syst. Signal Process.
Satyajit Bora, Roy Paily
2022 J jnl
Half-selection disturbance free 8T low leakage SRAM cell.
Int. J. Circuit Theory Appl.
Rohit Lorenzo, Roy Paily
2021 J jnl
A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Satyajit Bora, Roy Paily
2020 J jnl
An Efficient Architecture for QRS Detection in FPGA Using Integer Haar Wavelet Transform.
Circuits Syst. Signal Process.
Soham Talukder, Rajan Singh, Satyajit Bora, Roy Paily
2019 C conf
Analysis of Electromagnetic Actuation System for Different Coil Topologies.
TENCON
Pralay Chakrabarty, Siddhanta Roy, Roy Paily
2019 C conf
Fabrication of Back to Back Schottky Micro-Diodes Using Silver Nanoparticle Film and Zinc Oxide Nanowire Mat for Biological Interactions.
TENCON
Vimal Kumar Singh Yadav, Siddhanta Roy, Gayatri Natu, Roy Paily
2019 C conf
Low Power 10T SRAM Cell with Improved Stability Solving Soft Error Issue.
TENCON
Rohit Lorenzo, Roy Paily
2017 J jnl
Efficient Solar Power Management System for Self-Powered IoT Node.
IEEE Trans. Circuits Syst. I Regul. Pap.
Saroj Mondal, Roy Paily
2017 J jnl
Low-Power Digital Baseband Transceiver Design for UWB Physical Layer of IEEE 802.15.6 Standard.
IEEE Trans. Ind. Informatics
Manchi Pavan Kumar, Roy Paily, Anup Kumar Gogoi
2017 J jnl
On-Chip Photovoltaic Power Harvesting System With Low-Overhead Adaptive MPPT for IoT Nodes.
IEEE Internet Things J.
Saroj Mondal, Roy Paily
2016 J jnl
Analysis and design of moderate inversion based low power low-noise amplifier.
IET Comput. Digit. Tech.
Vinaya M. M., Roy Paily, Anil Mahanta
2016 Misc conf
Design and Implementation of Blind Assistance System Using Real Time Stereo Vision Algorithms.
VLSID
Vaddi Chandra Sekhar, Satyajit Bora, Monalisa Dash, Manchi Pavan Kumar, S. Josephine, Roy Paily
2016 Misc conf
Design and Implementation of Low-Power Digital Baseband Transceivers for IEEE802.15.6 Standard.
VLSID
Manchi Pavan Kumar, Roy Paily, Anup Kumar Gogoi
2016 J jnl
Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders.
Circuits Syst. Signal Process.
Rahul Shrestha, Roy Paily
2016 J jnl
Multi-standard high-throughput and low-power quasi-cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards.
IET Circuits Devices Syst.
Vijaya Kumar Kanchetla, Rahul Shrestha, Roy Paily
2016 Misc conf
Power Optimization of LNA for LTE Receiver.
VLSID
Vinaya M. M., Roy Paily, Anil Mahanta
2014 J jnl
Distributed Arithmetic based Split-Radix FFT.
J. Signal Process. Syst.
Sunil P. Joshi, Roy Paily
2014 — conf
Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-grouped Sliding-Window Technique.
ISED
Rahul Shrestha, Roy Paily
2013 — conf
An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network.
VDAT
R. K. Naga Mahesh, Akash Ganesan, Manchi Pavan Kumar, Roy Paily
2013 Misc conf
Gain, NF and IIP3 Budgeting of LTE Receiver Front End.
VLSI Design
Vinay M. M., Roy Paily, Anil Mahanta
2012 J jnl
Fpga Implementation of High Speed and Low Power Architectures for Image Segmentation using Sobel Operators.
J. Circuits Syst. Comput.
Abdul Raouf Khalid, Roy Paily
2011 — conf
Design of QRS Detection and Heart Rate Estimation System on FPGA.
ACC (4)
Sudheer Kurakula, A. S. D. P. Sudhansh, Roy Paily, Samarendra Dandapat
2008 A conf
A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning.
ISLPED
Depak Balemarthy, Roy Paily