Roy P. Paily

23 papers Misc 6Journal 10Unranked 7
YearRankTypeTitle / Venue / Authors
2026 J jnl
Hardware Efficient Approximate Convolution with Tunable Error Tolerance for CNNs.
CoRR
Vishal Shashidhar, Anupam Kumari, Roy P. Paily
2025 Misc conf
A Wide Dynamic Range Differential Drive CMOS Rectifier for μWatts RF Energy Harvesting Systems.
VLSID
Chaya Hegde, Arun Mohan, Saroj Mondal, Roy P. Paily
2025 Misc conf
Low Form-Factor Switchless Dual-Band Matching Network for RF Power Harvesting Systems.
VLSID
Arun Mohan, Saroj Mondal, Yash N. Rayudu, Roy P. Paily
2016 J jnl
An Efficient On-Chip Switched-Capacitor-Based Power Converter for a Microscale Energy Transducer.
IEEE Trans. Circuits Syst. II Express Briefs
Saroj Mondal, Roy P. Paily
2016 Misc conf
An Efficient on Chip Power Management Architecture for Solar Energy Harvesting Systems.
VLSID
Saroj Mondal, Roy P. Paily
2015 J jnl
A New PVT Compensation Technique Based on Current Comparison for Low-Voltage, Near Sub-Threshold LNA.
IEEE Trans. Circuits Syst. I Regul. Pap.
Vinaya M. M., Roy P. Paily, Anil Mahanta
2015 — conf
A low-power subthreshold LNA for mobile applications.
VDAT
Vinay M. M., Roy P. Paily, Anil Mahanta
2015 — conf
An efficient on-chip energy processing circuit for micro-scale energy harvesting systems.
VDAT
Saroj Mondal, Roy P. Paily
2015 J jnl
Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder.
J. Signal Process. Syst.
Rahul Shrestha, Roy P. Paily
2015 J jnl
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sachin Kumawat, Rahul Shrestha, Nikunj Daga, Roy P. Paily
2015 J jnl
VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder.
J. Low Power Electron.
Rahul Shrestha, Roy P. Paily
2014 — conf
An efficient hardware architecture for stereo disparity estimation.
VDAT
Fradaric Joseph, Kiran Francis, Archita Hore, Siddhanta Roy, S. Josephine, Roy P. Paily
2014 J jnl
Fabrication and Testing of an Osmotic Pressure Sensor for Glucose Sensing Application.
Micromachines
Nagesh Ch, Roy P. Paily
2014 J jnl
High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rahul Shrestha, Roy P. Paily
2013 — conf
A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance.
VDAT
Ratul Kumar Baruah, Roy P. Paily
2013 — conf
A novel state metric normalization technique for high-throughput maximum-a-posteriori-probability decoder.
ICACCI
Rahul Shrestha, Roy P. Paily
2013 Misc conf
Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding.
VLSI Design
Rahul Shrestha, Roy P. Paily
2013 J jnl
Performance and throughput analysis of turbo decoder for the physical layer of digitalvideo-broadcasting-satellite-services-tohandhelds standard.
IET Commun.
Rahul Shrestha, Roy P. Paily
2012 — conf
Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding.
VDAT
Rahul Shrestha, Roy P. Paily
2012 — conf
Low power 2.4 GHz RF transmitter for satellite subsystem using CORDIC based frequency translator.
WOCN
Amrita Brahmachari, Roy P. Paily
2011 J jnl
Fabrication and characterisation of high-performance and high-current back-gate thin-film field-effect transistors using sorted single-walled carbon nanotubes.
IET Circuits Devices Syst.
K. C. Narasimhamurthy, Roy P. Paily
2011 Misc conf
Performance Comparison of Thin-Film Transistors Fabricated Using Different Purity Semiconducting Nanotubes.
VLSI Design
K. C. Narasimhamurthy, Roy P. Paily
2009 Misc conf
Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects.
VLSI Design
K. C. Narasimhamurthy, Roy P. Paily