Rourab Paul - RankMe

41 papers C 1Misc 1Journal 36Unranked 3

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Trojan-Resilient NTT: Protecting Against Control Flow and Timing Faults on Reconfigurable Platforms. CoRR Rourab Paul, Krishnendu Guha, Amlan Chakrabarti
2025	J	`jnl`	Energy-Efficient NTT Sampler for Kyber Benchmarked on FPGA. CoRR Paresh Baidya, Rourab Paul, Vikas Srivastava, Sumit Kumar Debnath
2025	J	`jnl`	Error Detection Schemes for Barrett Reduction of CT-BU on FPGA in Post Quantum Cryptography. CoRR Paresh Baidya, Rourab Paul, Vikas Srivastava, Sumit Kumar Debnath
2025	J	`jnl`	LASSO-mCGA: Machine Learning and Modified Compact Genetic Algorithm-Based Biomarker Selection for Breast Cancer Subtype Classification. IEEE Access Nimisha Ghosh, Sankar Kumar Mridha, Rourab Paul
2025	J	`jnl`	Lightweight Fault Detection Architecture for NTT on FPGA. CoRR Rourab Paul, Paresh Baidya, Krishnendu Guha
2024	J	`jnl`	Blockchain based secret key management for trusted platform module standard in reconfigurable platform. Concurr. Comput. Pract. Exp. Rourab Paul, Nimisha Ghosh, Amrutanshu Panigrahi, Amlan Chakrabarti, Prasant Mohapatra
2024	J	`jnl`	Efficient Implementation of Knuth Yao Sampler on Reconfigurable Hardware. IEEE Comput. Archit. Lett. Paresh Baidya, Rourab Paul, Swagata Mandal, Sumit Kumar Debnath
2024	J	`jnl`	FastFlow in FPGA Stacks of Data Centers. CoRR Rourab Paul, Alberto Ottimo, Marco Danelutto
2024	J	`jnl`	Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Hardware Accelerator on Reconfigurable Architecture. IEEE Access Paresh Baidya, Swagata Mandal, Rourab Paul
2024	C	`conf`	Power Aware Scheduling of Tasks on FPGAs in Data Centers. PDP Rourab Paul, Marco Danelutto
2023	J	`jnl`	Power Aware Scheduling of Tasks on FPGAs in Data Centers. CoRR Rourab Paul, Marco Danelutto
2023	J	`jnl`	Smart contract assisted blockchain based public key infrastructure system. Trans. Emerg. Telecommun. Technol. Amrutanshu Panigrahi, Ajit Kumar Nayak, Rourab Paul
2022	J	`jnl`	CTB-PKI: Clustering and Trust Enabled Blockchain Based PKI System for Efficient Communication in P2P Network. IEEE Access Amrutanshu Panigrahi, Ajit Kumar Nayak, Rourab Paul, Bibhuprasad Sahu, Shashi Kant
2022	J	`jnl`	HealthCare EHR: A Blockchain-Based Decentralized Application. Int. J. Inf. Syst. Supply Chain Manag. Amrutanshu Panigrahi, Ajit Kumar Nayak, Rourab Paul
2022	J	`jnl`	Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture. CoRR Paresh Baidya, Swagata Mandal, Rourab Paul
2022	J	`jnl`	Smart Contract Assisted Blockchain based PKI System. CoRR Amrutanshu Panigrahi, Ajit Kumar Nayak, Rourab Paul
2021	J	`jnl`	Blockchain based secure smart city architecture using low resource IoTs. Comput. Networks Rourab Paul, Nimisha Ghosh, Suman Sau, Amlan Chakrabarti, Prasant Mohapatra
2021	J	`jnl`	Voltage Scaling for Partitioned Systolic Array in A Reconfigurable Platform. CoRR Rourab Paul, Sreetama Sarkar, Suman Sau, Koushik Chakraborty, Sanghamitra Roy, Amlan Chakrabarti
2020	J	`jnl`	The Blockchain Based Auditor on Secret key Life Cycle in Reconfigurable Platform. CoRR Rourab Paul, Nimisha Ghosh, Amlan Chakrabarti, Prasant Mahapatra
2020	J	`jnl`	iDCR: Improved Dempster Combination Rule for Multisensor Fault Diagnosis. CoRR Nimisha Ghosh, Sayantan Saha, Rourab Paul
2019	J	`jnl`	Fault Matters: Sensor Data Fusion for Detection of Faults using Dempster-Shafer Theory of Evidence in IoT-Based Applications. CoRR Nimisha Ghosh, Rourab Paul, Satyabrata Maity, Krishanu Maity, Sayantan Saha
2019	J	`jnl`	IoT based Smart Access Controlled Secure Smart City Architecture Using Blockchain. CoRR Rourab Paul, Nimisha Ghosh, Suman Sau, Amlan Chakrabarti, Prasant Mahapatra
2018	J	`jnl`	Hardware variant NSP with security-aware automated preferential algorithm. IET Comput. Digit. Tech. Rourab Paul, Gitesh Sikder, Amlan Chakrabarti, Ranjan Ghosh
2018	J	`jnl`	Partitioned security processor architecture on FPGA platform. IET Comput. Digit. Tech. Rourab Paul, Sandeep K. Shukla
2017	—	`conf`	A High Speed KECCAK Coprocessor for Partitioned NSP Architecture on FPGA Platform. VDAT Rourab Paul, Sandeep Kumar Shukla
2017	J	`jnl`	Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware. Microprocess. Microsystems Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay
2016	J	`jnl`	A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code. IEEE Embed. Syst. Lett. Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay
2016	J	`jnl`	Accelerating More Secure RC4 : Implementation of Seven FPGA Designs in Stages upto 8 byte per clock. CoRR Rourab Paul, Hemanta Dey, Amlan Chakrabarti, Ranjan Ghosh
2016	Misc	`conf`	Error Resilient Secure Multi-gigabit Optical Link Design for High Energy Physics Experiment. VLSID Jubin Mitra, Shuaib Ahmad Khan, Rourab Paul, Sanjoy Mukherjee, Amlan Chakrabarti, Tapan Kumar Nayak
2016	J	`jnl`	Multi core SSL/TLS security processor architecture and its FPGA prototype design with automated preferential algorithm. Microprocess. Microsystems Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh
2015	J	`jnl`	A Novel Method for Soft Error Mitigation in FPGA using Adaptive Cross Parity Code. CoRR Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay
2015	—	`conf`	Multicore encryption and authentication on a reconfigurable hardware. ReTIS Saheli Ghosh, Subha Jyoti Das, Rourab Paul, Amlan Chakrabarti
2014	J	`jnl`	Fault Detection for RC4 Algorithm and its Implementation on FPGA Platform. CoRR Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh
2014	J	`jnl`	Hardware Implementation of four byte per clock RC4 algorithm. CoRR Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh
2014	J	`jnl`	Multi Core SSL/TLS Security Processor Architecture Prototype Design with automated Preferential Algorithm in FPGA. CoRR Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh
2014	J	`jnl`	Performance Evaluation of ECC in Single and Multi Processor Architectures on FPGA Based Embedded System. CoRR Sruti Agarwal, Sangeet Saha, Rourab Paul, Amlan Chakrabarti
2012	J	`jnl`	A brief experience on journey through hardware developments for image processing and its applications on Cryptography CoRR Sangeet Saha, Chandrajit Pal, Rourab Paul, Satyabrata Maity, Suman Sau
2012	—	`conf`	A novel AES-256 implementation on FPGA using co-processor based architecture. ICACCI Suman Sau, Rourab Paul, Tanmay Biswas, Amlan Chakrabarti
2012	J	`jnl`	A simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication CoRR Rourab Paul, Sangeet Saha, J. K. M. Sadique Uz Zaman, Suman Das, Amlan Chakrabarti, Ranjan Ghosh
2012	J	`jnl`	Architecture for real time continuous sorting on large width data volume for fpga based applications CoRR Rourab Paul, Suman Sau, Amlan Chakrabarti
2012	J	`jnl`	Design and implementation of real time AES-128 on real time operating system for multiple FPGA communication CoRR Rourab Paul, Sangeet Saha, Suman Sau, Amlan Chakrabarti