Roshan Weerasekera

32 papers A 4C 1Misc 1Journal 11Unranked 13

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	NL2GDS: LLM-aided interface for Open Source Chip Design. CoRR Max Eland, Jeyan Thiyagalingam, Dinesh Pamunuwa, Roshan Weerasekera
2025	—	`conf`	DT2HDL: A Binary Decision Tree to HDL Generation Tool. ISQED Qijia Tang, Dinesh Pamunuwa, Roshan Weerasekera
2025	A	`conf`	Nanoelectromechanical Binary Comparator for Edge-Computing Applications. DATE Victor Marot, Manu Bala Krishnan, Mukesh Kumar Kulsreshath, Elliott Worsey, Roshan Weerasekera, Dinesh Pamunuwa
2024	J	`jnl`	Incident and Load Power Relations in a Mismatched Lossless Transmission Line. Circuits Syst. Signal Process. Disala Uduwawala, Roshan Weerasekera
2024	J	`jnl`	Machine Learning Assisted Postural Movement Recognition using Photoplethysmography(PPG). CoRR Robbie Maccay, Roshan Weerasekera
2023	—	`ch.`	Electrical Signal Transfer by Fungi. Fungal Machines Neil Phillips, Roshan Weerasekera, Nic Roberts, Andrew Adamatzky
2023	J	`jnl`	Propagation of electrical signals by fungi. Biosyst. Richard Mayne, Nic Roberts, Neil Phillips, Roshan Weerasekera, Andrew Adamatzky
2023	J	`jnl`	Propagation of electrical signals by fungi. CoRR Richard Mayne, Nic Roberts, Neil Phillips, Roshan Weerasekera, Andrew Adamatzky
2019	J	`jnl`	Neuromorphic Liquid Marbles With Aqueous Carbon Nanotube Cores. CoRR Richard Mayne, Thomas C. Draper, Neil Phillips, James Gerald Holland Whiting, Roshan Weerasekera, Claire Fullarton, Ben P. J. de Lacy Costello, Andrew Adamatzky
2018	J	`jnl`	Excitable London: Street map analysis with Oregonator model. CoRR Andrew Adamatzky, Neil Phillips, Roshan Weerasekera, Michail-Antisthenis I. Tsompanas, Georgios Ch. Sirakoulis
2015	J	`jnl`	BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Chao Wang, Jun Zhou, Roshan Weerasekera, Bin Zhao, Xin Liu, Philippe Royannez, Minkyu Je
2015	J	`jnl`	Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC-TSI). IEEE Des. Test Guruprasad Katti, S. W. Ho, Li Hong Yu, Songbai Zhang, Rahul Dutta, Roshan Weerasekera, Ka-Fai Chang, Jong-Kai Lin, Srinivasa Rao Vempati, Surya Bhattacharya
2013	—	`conf`	High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer. 3DIC Jiacheng Wang, Shunli Ma, Sai Manoj Pudukotai Dinakarrao, Mingbin Yu, Roshan Weerasekera, Hao Yu
2011	C	`conf`	3-D integration and the limits of silicon computation. VLSI-SoC Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch
2011	—	`conf`	Design exploration of 3D stacked non-volatile memory by conductive bridge based crossbar. 3DIC Yuhao Wang, Chun Zhang, Revanth Nadipalli, Hao Yu, Roshan Weerasekera
2011	—	`conf`	Interconnect design and analysis for Through Silicon Interposers (TSIs). 3DIC Joseph Romen Cubillo, Roshan Weerasekera, Zaw Zaw Oo, En-Xiao Liu, Bob Conn, Surya Bhattacharya, Robert Patti
2011	A	`conf`	Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. ICCAD Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa
2011	—	`conf`	Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks. NOCS Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa, Axel Jantsch, Awet Yemane Weldezion
2010	A	`conf`	On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. DATE Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen
2009	—	`conf`	3-D memory organization and performance analysis for multi-processor network-on-chip architecture. 3DIC Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerasekera, Hannu Tenhunen
2009	—	`conf`	Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. 3DIC Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen, Li-Rong Zheng
2009	—	`conf`	Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. 3DIC Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen
2009	—	`conf`	Scalability of network-on-chip communication architecture for 3-D meshes. NOCS Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen
2009	J	`jnl`	Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
2008	J	`jnl`	Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. IEEE Trans. Very Large Scale Integr. Syst. Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
2008	—	`—`	System Interconnection Design Trade-offs in Three-Dimensional (3-D) Integrated Circuits. Roshan Weerasekera
2007	Misc	`conf`	Delay-Balanced Smart Repeaters for On-Chip Global Signaling. VLSI Design Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
2007	—	`conf`	Early selection of system implementation choice among SoC, SoP and 3-D Integration. SoCC Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
2007	A	`conf`	Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. ICCAD Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
2006	—	`conf`	Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. SLIP Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
2005	—	`conf`	Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. PATMOS Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
2004	—	`conf`	Crosstalk immune interconnect driver design. SoC Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen