Ronny Ronen - RankMe

70 papers A* 12A 4C 4Misc 1Journal 40Unranked 9

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Preprocessing Methods for Memristive Reservoir Computing for Image Recognition. MetroXRAINE Rishona Daniels, Duna Wattad, Ronny Ronen, David Saad, Shahar Kvatinsky
2025	J	`jnl`	Preprocessing Methods for Memristive Reservoir Computing for Image Recognition. CoRR Rishona Daniels, Duna Wattad, Ronny Ronen, David Saad, Shahar Kvatinsky
2024	J	`jnl`	Accelerating DNA Read Mapping with Digital Processing-in-Memory. CoRR Rotem Ben Hur, Orian Leitersdorf, Ronny Ronen, Lidor Goldshmidt, Idan Magram, Lior Kaplun, Leonid Yavitz, Shahar Kvatinsky
2024	A*	`conf`	PyPIM: Integrating Digital Processing-in-Memory from Microarchitectural Design to Python Tensors. MICRO Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2024	J	`jnl`	Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. IEEE Trans. Emerg. Top. Comput. Ben Perach, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky
2023	—	`conf`	Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory. NEWCAS Ben Perach, Ronny Ronen, Shahar Kvatinsky
2023	J	`jnl`	Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory. CoRR Ben Perach, Ronny Ronen, Shahar Kvatinsky
2023	J	`jnl`	AritPIM: High-Throughput In-Memory Arithmetic. IEEE Trans. Emerg. Top. Comput. Orian Leitersdorf, Dean Leitersdorf, Jonathan Gal, Mor M. Dahan, Ronny Ronen, Shahar Kvatinsky
2023	J	`jnl`	CUDA-PIM: End-to-End Integration of Digital Processing-in-Memory from High-Level C++ to Microarchitectural Design. CoRR Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2023	J	`jnl`	ConvPIM: Evaluating Digital Processing-in-Memory through Convolutional Neural Network Acceleration. CoRR Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2023	—	`conf`	Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. SOCC Ben Perach, Ronny Ronen, Shahar Kvatinsky
2023	J	`jnl`	Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. CoRR Ben Perach, Ronny Ronen, Shahar Kvatinsky
2023	J	`jnl`	FourierPIM: High-Throughput In-Memory Fast Fourier Transform and Polynomial Multiplication. CoRR Orian Leitersdorf, Yahav Boneh, Gonen Gazit, Ronny Ronen, Shahar Kvatinsky
2023	A*	`conf`	On Consistency for Bulk-Bitwise Processing-in-Memory. HPCA Ben Perach, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	AritPIM: High-Throughput In-Memory Arithmetic. CoRR Orian Leitersdorf, Dean Leitersdorf, Jonathan Gal, Mor M. Dahan, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices. Adv. Intell. Syst. Wei Wang, Barak Hoffer, Tzofnat Greenberg-Toledo, Yang Li, Minhui Zou, Eric Herbelin, Ronny Ronen, Xiaoxin Xu, Yulin Zhao, Jianguo Yang, Shahar Kvatinsky
2022	J	`jnl`	Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices. CoRR Wei Wang, Barak Hoffer, Tzofnat Greenberg-Toledo, Yang Li, Minhui Zou, Eric Herbelin, Ronny Ronen, Xiaoxin Xu, Yulin Zhao, Jianguo Yang, Shahar Kvatinsky
2022	J	`jnl`	FiltPIM: In-Memory Filter for DNA Sequencing. CoRR Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky
2022	—	`conf`	HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory. MOCAST Batel Oved, Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory. CoRR Batel Oved, Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2022	C	`conf`	MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic. ISCAS Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic. CoRR Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	MultPIM: Fast Stateful Multiplication for Processing-in-Memory. IEEE Trans. Circuits Syst. II Express Briefs Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	On Consistency for Bulk-Bitwise Processing-in-Memory. CoRR Ben Perach, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. CoRR Ben Perach, Ronny Ronen, Benny Kimelfeld, Shahar Kvatinsky
2022	J	`jnl`	PartitionPIM: Practical Memristive Partitions for Fast Processing-in-Memory. CoRR Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2022	J	`jnl`	The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems. ACM J. Emerg. Technol. Comput. Syst. Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky
2022	J	`jnl`	abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory. CoRR Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky
2021	A*	`conf`	Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. DAC Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky
2021	J	`jnl`	Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. CoRR Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky
2021	—	`conf`	FiltPIM: In-Memory Filter for DNA Sequencing. ICECS Marcel Khalifa, Rotem Ben Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, Shahar Kvatinsky
2021	—	`conf`	Making Memristive Processing-in-Memory Reliable. ICECS Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2021	J	`jnl`	Making Memristive Processing-in-Memory Reliable. CoRR Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2021	J	`jnl`	MultPIM: Fast Stateful Multiplication for Processing-in-Memory. CoRR Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2021	J	`jnl`	The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems. CoRR Ronny Ronen, Adi Eliahu, Orian Leitersdorf, Natan Peled, Kunal Korgaonkar, Anupam Chattopadhyay, Ben Perach, Shahar Kvatinsky
2021	J	`jnl`	multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures. ACM J. Emerg. Technol. Comput. Syst. Adi Eliahu, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky
2020	A	`conf`	CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. ICCAD Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky
2020	J	`jnl`	CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. CoRR Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky
2020	J	`jnl`	SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rotem Ben Hur, Ronny Ronen, Ameer Haj Ali, Debjyoti Bhattacharjee, Adi Eliahu, Natan Peled, Shahar Kvatinsky
2020	C	`conf`	X-MAGIC: Enhancing PIM Using Input Overwriting Capabilities. VLSI-SOC Natan Peled, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky
2020	—	`conf`	abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory. VLSI-SoC (Selected Papers) Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky
2020	C	`conf`	abstractPIM: Bridging the Gap Between Processing-In-Memory Technology and Instruction Set Architecture. VLSI-SOC Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky
2019	J	`jnl`	CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM. IEEE Micro Nishil Talati, Heonjae Ha, Ben Perach, Ronny Ronen, Shahar Kvatinsky
2019	J	`jnl`	The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm. CoRR Kunal Korgaonkar, Ronny Ronen, Anupam Chattopadhyay, Shahar Kvatinsky
2018	J	`jnl`	IMAGING: In-Memory AlGorithms for Image processiNG. IEEE Trans. Circuits Syst. I Regul. Pap. Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Shahar Kvatinsky
2018	J	`jnl`	Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing. IEEE Micro Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Shahar Kvatinsky
2018	A	`conf`	Practical challenges in delivering the promises of real processing-in-memory machines. DATE Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky
2017	J	`jnl`	Why & When Deep Learning Works: Looking Inside Deep Learnings. CoRR Ronny Ronen
2014	A*	`conf`	Improving the energy efficiency of Big Cores. ISCA Kenneth Czechowski, Victor W. Lee, Ed Grochowski, Ronny Ronen, Ronak Singhal, Richard W. Vuduc, Pradeep Dubey
2010	A*	`ed.`	37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France ISCA André Seznec, Uri C. Weiser, Ronny Ronen
2009	—	`conf`	Larrabee: a many-core Intel architecture for visual computing. Conf. Computing Frontiers Ronny Ronen
2009	A*	`conf`	Programming model for a heterogeneous x86 platform. PLDI Bratin Saha, Xiaocheng Zhou, Hu Chen, Ying Gao, Shoumeng Yan, Mohan Rajagopalan, Jesse Fang, Peinan Zhang, Ronny Ronen, Avi Mendelson
2009	J	`jnl`	Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture. IEEE Trans. Circuits Syst. II Express Briefs Amit Golander, Shlomo Weiss, Ronny Ronen
2009	Misc	`conf`	Terascale chip multiprocessor memory hierarchy and programming model. HiPC Shoumeng Yan, Xiaocheng Zhou, Ying Gao, Hu Chen, Sai Luo, Peinan Zhang, Naveen Cherukuri, Ronny Ronen, Bratin Saha
2008	J	`jnl`	DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals. IEEE Comput. Archit. Lett. Amit Golander, Shlomo Weiss, Ronny Ronen
2007	J	`jnl`	Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences. IEEE Micro Ronny Ronen, Antonio González
2004	C	`conf`	Best of Both Latency and Throughput. ICCD Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang
2003	J	`jnl`	Micro-operation cache: a power aware frontend for variable instruction length ISA. IEEE Trans. Very Large Scale Integr. Syst. Baruch Solomon, Avi Mendelson, Ronny Ronen, Doron Orenstein, Yoav Almog
2003	J	`jnl`	On Estimating Optimal Performance of CPU Dynamic Thermal Management. IEEE Comput. Archit. Lett. Aviad Cohen, Lev Finkelstein, Avi Mendelson, Ronny Ronen, Dmitry Rudoy
2003	A	`conf`	Selecting long atomic traces for high coverage. ICS Roni Rosner, Micha Moffie, Yiannakis Sazeides, Ronny Ronen
2001	J	`jnl`	Coming challenges in microarchitecture and architecture. Proc. IEEE Ronny Ronen, Avi Mendelson, Konrad Lai, Shih-Lien Lu, Fred J. Pollack, John Paul Shen
2001	J	`jnl`	Dynamic techniques for load and load-use scheduling. Proc. IEEE Amir Roth, Ronny Ronen, Avi Mendelson
2001	—	`conf`	Filtering Techniques to Improve Trace-Cache Efficiency. IEEE PACT Roni Rosner, Avi Mendelson, Ronny Ronen
2001	A	`conf`	Micro-operation cache: a power aware frontend for the variable instruction length ISA. ISLPED Baruch Solomon, Avi Mendelson, Doron Orenstein, Yoav Almog, Ronny Ronen
2000	A*	`conf`	Early load address resolution via register tracking. ISCA Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stéphan Jourdan, Maxim Kalaev, Ronny Ronen
2000	A*	`conf`	eXtended Block Cache. HPCA Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen
1999	A*	`conf`	Correlated Load-Address Predictors. ISCA Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri C. Weiser
1999	A*	`ed.`	Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999 MICRO Ronny Ronen, Matthew K. Farrens, Ilan Y. Spillinger
1999	A*	`conf`	Speculation Techniques for Improving Load Related Instruction Scheduling. ISCA Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan Jourdan
1998	A*	`conf`	A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification. MICRO Stéphan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz