Rongliang Fu - RankMe

28 papers A* 3A 8B 1Journal 8Unranked 8

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	DCLOG: Don't Cares-based Logic Optimization using Pre-training Graph Neural Networks. ASP-DAC Rongliang Fu, Libo Shen, Ziyi Wang, Zhengxing Lei, Zixiao Wang, JunYing Huang, Bei Yu, Tsung-Yi Ho
2026	J	`jnl`	JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits. IEEE Trans. Computers Rongliang Fu, Minglei Zhou, Siyan Chen, Xinda Chen, JunYing Huang, Xiaochun Ye, Zhimin Zhang, Tsung-Yi Ho
2026	—	`conf`	Partitioning-free 3D-IC Floorplanning. ASP-DAC Shuo Ren, Zhen Zhuang, Rongliang Fu, Leilei Jin, Libo Shen, Bei Yu, Tsung-Yi Ho
2026	J	`jnl`	Towards Secure and Efficient DNN Accelerators via Hardware-Software Co-Design. CoRR Wei Xuan, Zihao Xuan, Rongliang Fu, Ning Lin, Kwunhang Wong, Zikang Yuan, Lang Feng, Zhongrui Wang, Tsung-Yi Ho, Yuzhong Jiao, Luhong Liang
2025	—	`conf`	An Optimal DFF-Oriented Technology Legalization Algorithm for Rapid Single-Flux-Quantum Circuits. ACM Great Lakes Symposium on VLSI Minglei Zhou, Rongliang Fu, Ran Zhang, Xiaochun Ye, Tsung-Yi Ho, JunYing Huang
2025	J	`jnl`	Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rongliang Fu, Mengmeng Wang, Yirong Kan, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Tsung-Yi Ho
2025	A	`conf`	ChronoTE: Crosstalk-Aware Timing Estimation for Routing Optimization via Edge-Enhanced GNNs. ICCAD Leilei Jin, Rongliang Fu, Zhen Zhuang, Liang Xiao, Fangzhou Liu, Bei Yu, Tsung-Yi Ho
2025	J	`jnl`	Efficient Cartesian Genetic Programming-Based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rongliang Fu, Robert Wille, Nobuyuki Yoshikawa, Tsung-Yi Ho
2025	—	`conf`	HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning. ISPD Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, Bei Yu
2025	A	`conf`	J2Place: A Multiphase Clocking-Oriented Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. ICCAD Rongliang Fu, Minglei Zhou, Huilong Jiang, JunYing Huang, Xiaochun Ye, Tsung-Yi Ho
2025	A	`conf`	JBSA: A Bit-Serial Accelerator for Deep Neural Networks Using Superconducting SFQ Logic. ICS Yang Su, Sheng Li, Huilong Jiang, Haofei Yin, Rongliang Fu, JunYing Huang, Xiaochun Ye, Zhimin Zhang, Jie Ren, Xiaoping Gao, Tsung-Yi Ho, Dongrui Fan
2025	A*	`conf`	Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision. DAC Rongliang Fu, Ran Zhang, Ziyang Zheng, Zhengyuan Shi, Yuan Pu, JunYing Huang, Qiang Xu, Tsung-Yi Ho
2025	A*	`conf`	SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy. DAC Wei Xuan, Zhongrui Wang, Lang Feng, Ning Lin, Zihao Xuan, Rongliang Fu, Tsung-Yi Ho, Yuzhong Jiao, Luhong Liang
2025	J	`jnl`	SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy. CoRR Wei Xuan, Zhongrui Wang, Lang Feng, Ning Lin, Zihao Xuan, Rongliang Fu, Tsung-Yi Ho, Yuzhong Jiao, Luhong Liang
2025	J	`jnl`	TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rongliang Fu, Chao Wang, Bei Yu, Tsung-Yi Ho
2024	B	`conf`	FlatDD: A High-Performance Quantum Circuit Simulator using Decision Diagram and Flat Array. ICPP Shui Jiang, Rongliang Fu, Lukas Burgholzer, Robert Wille, Tsung-Yi Ho, Tsung-Wei Huang
2024	A	`conf`	JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. DATE Siyan Chen, Rongliang Fu, JunYing Huang, Zhimin Zhang, Xiaochun Ye, Tsung-Yi Ho, Dongrui Fan
2024	A	`conf`	RABER: Reliability-Aware Bayesian-Optimization-based Control Layer Escape Routing for Flow-based Microfluidics. ICCAD Siyuan Liang, Rongliang Fu, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho
2024	A*	`conf`	RCGP: An Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits based on Efficient Cartesian Genetic Programming. DAC Rongliang Fu, Robert Wille, Tsung-Yi Ho
2023	—	`conf`	A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits. ASP-DAC Rongliang Fu, Mengmeng Wang, Yirong Kan, Nobuyuki Yoshikawa, Tsung-Yi Ho, Olivia Chen
2023	A	`conf`	BOMIG: A Majority Logic Synthesis Framework for AQFP Logic. DATE Rongliang Fu, JunYing Huang, Mengmeng Wang, Nobuyuki Yoshikawa, Bei Yu, Tsung-Yi Ho, Olivia Chen
2023	A	`conf`	DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits. ICCAD Rongliang Fu, Olivia Chen, Bei Yu, Nobuyuki Yoshikawa, Tsung-Yi Ho
2023	A	`conf`	Exact Logic Synthesis for Reversible Quantum-Flux-Parametron Logic. ICCAD Rongliang Fu, Olivia Chen, Nobuyuki Yoshikawa, Tsung-Yi Ho
2023	—	`conf`	JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits. ACM Great Lakes Symposium on VLSI Xinda Chen, Rongliang Fu, JunYing Huang, Huawei Cao, Zhimin Zhang, Xiaochun Ye, Tsung-Yi Ho, Dongrui Fan
2022	J	`jnl`	A survey on superconducting computing technology: circuits, architectures and design tools. CCF Trans. High Perform. Comput. JunYing Huang, Rongliang Fu, Xiaochun Ye, Dongrui Fan
2022	J	`jnl`	JBNN: A Hardware Design for Binarized Neural Networks Using Single-Flux-Quantum Circuits. IEEE Trans. Computers Rongliang Fu, JunYing Huang, Haibin Wu, Xiaochun Ye, Dongrui Fan, Tsung-Yi Ho
2021	—	`conf`	Equivalence Checking for Superconducting RSFQ Logic Circuits. ACM Great Lakes Symposium on VLSI Rongliang Fu, JunYing Huang, Zhimin Zhang
2020	—	`conf`	Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits. ACM Great Lakes Symposium on VLSI Rongliang Fu, Zhimin Zhang, Guang-Ming Tang, JunYing Huang, Xiaochun Ye, Dongrui Fan, Ninghui Sun