Rongjin Xu

13 papers C 2Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2025 J jnl
An Integer-N Reference-Double-Sampling PLL for Frequency-Multiplied Octa-Phase Clock Generation Achieving -251.9 dB FOM
IEEE Trans. Circuits Syst. I Regul. Pap.
Sirou Li, Rongjin Xu, Weijia Zeng, Kaiyun Cao, Heyu Ren, Xing Wu, Liangjian Lyu, C.-J. Richard Shi
2022 — conf
A 0.021mm
ISSCC
Rongjin Xu, Dawei Ye, Sirou Li, Chuanjin Richard Shi
2022 J jnl
A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction.
Integr.
Rongjin Xu, Dawei Ye, Chuanjin Richard Shi
2022 J jnl
Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rongjin Xu, Dawei Ye, Chuanjin Richard Shi
2022 J jnl
Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain".
IEEE J. Solid State Circuits
Dawei Ye, Rongjin Xu, Chuanjin Richard Shi
2021 J jnl
A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain.
IEEE J. Solid State Circuits
Dawei Ye, Rongjin Xu, Chuanjin Richard Shi
2021 — conf
A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference.
A-SSCC
Dawei Ye, Yuting Tu, Wenjun Gong, Rongjin Xu, Chuanjin Richard Shi
2020 C conf
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification.
ISCAS
Yuting Tu, Rongjin Xu, Dawei Ye, Liangjian Lyu, Chuanjin Richard Shi
2020 J jnl
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission.
IEEE Trans. Circuits Syst. II Express Briefs
Liangjian Lyu, Dawei Ye, Rongjin Xu, Geng Mu, Heng Zhao, Yingfei Xiang, Yuting Tu, Yiyun Zhang, Chuanjin Richard Shi
2019 C conf
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer.
ISCAS
Dawei Ye, Rongjin Xu, Liangjian Lyu, Chuanjin Richard Shi
2019 — conf
A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity.
ISSCC
Dawei Ye, Rongjin Xu, Chuanjin Richard Shi
2015 — conf
100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array.
ASICON
Jingjing Wang, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren
2015 — conf
A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network.
ASICON
Rongjin Xu, Yongzhen Chen, Mingshuo Wang, Ning Li, Fan Ye, Junyan Ren