Rong-Jyi Yang

13 papers Journal 11Unranked 2
YearRankTypeTitle / Venue / Authors
2016 J jnl
A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM.
IEEE Trans. Very Large Scale Integr. Syst.
Wei-Cheng Chen, Chao-Chyun Chen, Chia-Yu Yao, Rong-Jyi Yang
2015 J jnl
Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line.
IEEE Trans. Very Large Scale Integr. Syst.
Chia-Yu Yao, Yung-Hsiang Ho, Yi-Yao Chiu, Rong-Jyi Yang
2012 — conf
A wide-range all-digital delay-locked loop using fast-lock variable SAR algorithm.
ISPACS
Wei-Cheng Chen, Rong-Jyi Yang, Chia-Yu Yao, Chao-Chyun Chen
2008 — conf
A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition.
APCCAS
Chi-Shuang Oulee, Rong-Jyi Yang
2008 J jnl
An All-Digital Fast-Locking Programmable DLL-Based Clock Generator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chuan-Kang Liang, Rong-Jyi Yang, Shen-Iuan Liu
2007 J jnl
A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS Technology.
IEEE J. Solid State Circuits
Rong-Jyi Yang, Shen-Iuan Liu
2007 J jnl
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm.
IEEE J. Solid State Circuits
Rong-Jyi Yang, Shen-Iuan Liu
2006 J jnl
A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit.
IEEE J. Solid State Circuits
Rong-Jyi Yang, Kuan-Hua Chao, Sy-Chyuan Hwu, Chuan-Kang Liang, Shen-Iuan Liu
2006 J jnl
A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuit.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rong-Jyi Yang, Kuan-Hua Chao, Shen-Iuan Liu
2005 J jnl
A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector.
IEICE Trans. Electron.
Rong-Jyi Yang, Shen-Iuan Liu
2005 J jnl
A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs.
IEICE Trans. Electron.
Rong-Jyi Yang, Shen-Iuan Liu
2004 J jnl
A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet.
IEEE J. Solid State Circuits
Rong-Jyi Yang, Shang-Ping Chen, Shen-Iuan Liu
2004 J jnl
Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hsiang-Hui Chang, Rong-Jyi Yang, Shen-Iuan Liu