Ronald G. Dreslinski

151 papers A* 34A 16B 11C 6Misc 3Journal 52Unranked 28

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET. IEEE J. Solid State Circuits Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw
2025	J	`jnl`	Mayura: Exploiting Similarities in Motifs for Temporal Co-Mining. CoRR Sanjay Sri Vallabh Singapuram, Ronald G. Dreslinski, Nishil Talati
2025	J	`jnl`	Mayura: Exploiting Similarities in Motifs for Temporal Co-Mining. Proc. VLDB Endow. Sanjay Sri Vallabh Singapuram, Ronald G. Dreslinski, Nishil Talati
2025	A*	`conf`	NMP-PaK: Near-Memory Processing Acceleration of Scalable De Novo Genome Assembly. ISCA Heewoo Kim, Sanjay Sri Vallabh Singapuram, Haojie Ye, Joseph Izraelevitz, Trevor N. Mudge, Ronald G. Dreslinski, Nishil Talati
2025	J	`jnl`	NMP-PaK: Near-Memory Processing Acceleration of Scalable De Novo Genome Assembly. CoRR Heewoo Kim, Sanjay Sri Vallabh Singapuram, Haojie Ye, Joseph Izraelevitz, Trevor N. Mudge, Ronald G. Dreslinski, Nishil Talati
2024	J	`jnl`	Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication. ACM Trans. Reconfigurable Technol. Syst. Kuan-Yu Chen, Thomas Mason Nelson, Alireza Khadem, Morteza Fayazi, Sanjay Sri Vallabh Singapuram, Ronald G. Dreslinski, Nishil Talati, Hun-Seok Kim, David T. Blaauw
2024	J	`jnl`	FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs). IEEE Des. Test Anish Krishnakumar, Hanguang Yu, Tutu Ajayi, A. Alper Goksoy, Vishrut Pandey, Joshua Mack, Md Sahil Hassan, Kuan-Yu Chen, Chaitali Chakrabarti, Daniel W. Bliss, Ali Akoglu, Hun-Seok Kim, Ronald G. Dreslinski, David T. Blaauw, Ümit Y. Ogras
2023	J	`jnl`	Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher. CoRR Yichen Yang, Jingtao Li, Nishil Talati, Subhankar Pal, Siying Feng, Chaitali Chakrabarti, Trevor N. Mudge, Ronald G. Dreslinski
2023	J	`jnl`	AnGeL: Fully-Automated Analog Circuit Generator Using a Neural Network Assisted Semi-Supervised Learning Approach. IEEE Trans. Circuits Syst. I Regul. Pap. Morteza Fayazi, Morteza Tavakoli Taba, Ehsan Afshari, Ronald G. Dreslinski
2023	A	`conf`	Chex-Mix: Combining Homomorphic Encryption with Trusted Execution Environments for Oblivious Inference in the Cloud. EuroS&P Deepika Natarajan, Andrew D. Loveless, Wei Dai, Ronald G. Dreslinski
2023	J	`jnl`	CrossTalk: Making Low-Latency Fault Tolerance Cheap by Exploiting Redundant Networks. ACM Trans. Embed. Comput. Syst. Andrew D. Loveless, Linh Thi Xuan Phan, Lisa Erickson, Ronald G. Dreslinski, Baris Kasikci
2023	J	`jnl`	Demystifying Graph Sparsification Algorithms in Graph Properties Preservation. CoRR Yuhan Chen, Haojie Ye, Sanketh Vedula, Alex M. Bronstein, Ronald G. Dreslinski, Trevor N. Mudge, Nishil Talati
2023	J	`jnl`	Demystifying Graph Sparsification Algorithms in Graph Properties Preservation. Proc. VLDB Endow. Yuhan Chen, Haojie Ye, Sanketh Vedula, Alex M. Bronstein, Ronald G. Dreslinski, Trevor N. Mudge, Nishil Talati
2023	A	`conf`	FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method. ICCAD Morteza Fayazi, Morteza Tavakoli Taba, Amirata Tabatabavakili, Ehsan Afshari, Ronald G. Dreslinski
2023	J	`jnl`	FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method. CoRR Morteza Fayazi, Morteza Tavakoli Taba, Amirata Tabatabavakili, Ehsan Afshari, Ronald G. Dreslinski
2023	—	`conf`	GRACE: A Scalable Graph-Based Approach to Accelerating Recommendation Model Inference. ASPLOS (3) Haojie Ye, Sanketh Vedula, Yuhan Chen, Yichen Yang, Alex M. Bronstein, Ronald G. Dreslinski, Trevor N. Mudge, Nishil Talati
2023	J	`jnl`	MTrainS: Improving DLRM training efficiency using heterogeneous memories. CoRR Hiwot Tadese Kassa, Paul Johnson, Jason Akers, Mrinmoy Ghosh, Andrew Tulloch, Dheevatsa Mudigere, Jongsoo Park, Xing Liu, Ronald G. Dreslinski, Ehsan K. Ardestani
2023	J	`jnl`	Open Information Extraction: A Review of Baseline Techniques, Approaches, and Applications. CoRR Serafina Kamp, Morteza Fayazi, Zineb Benameur-El Youbi, Shuyan Yu, Ronald G. Dreslinski
2023	A*	`conf`	PCSPOOF: Compromising the Safety of Time-Triggered Ethernet. SP Andrew D. Loveless, Linh Thi Xuan Phan, Ronald G. Dreslinski, Baris Kasikci
2023	A	`conf`	RecPIM: A PIM-Enabled DRAM-RRAM Hybrid Memory System For Recommendation Models. ISLPED Heewoo Kim, Haojie Ye, Trevor N. Mudge, Ronald G. Dreslinski, Nishil Talati
2023	J	`jnl`	Rethinking DRAM's Page Mode With STT-MRAM. IEEE Trans. Computers Byoungchan Oh, Nilmini Abeyratne, Nam Sung Kim, Jeongseob Ahn, Ronald G. Dreslinski, Trevor N. Mudge
2022	—	`conf`	A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET. VLSI Technology and Circuits Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw
2022	J	`jnl`	A Holistic Solution for Reliability of 3D Parallel Systems. ACM J. Emerg. Technol. Comput. Syst. Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald G. Dreslinski
2022	A	`conf`	A Unified Forward Error Correction Accelerator for Multi-Mode Turbo, LDPC, and Polar Decoding. ISLPED Yufan Yue, Tutu Ajayi, Xueyang Liu, Peiwen Xing, Zihan Wang, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
2022	J	`jnl`	An Architecture to Accelerate Computation on Encrypted Data. IEEE Micro Axel Feldmann, Nikola Samardzic, Aleksandar Krastev, Srinivas Devadas, Ronald G. Dreslinski, Chris Peikert, Daniel Sánchez
2022	C	`conf`	Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor. ISCAS Daniel W. Bliss, Tutu Ajayi, Ali Akoglu, Ilkin Aliyev, Toygun Basaklar, Leul Belayneh, David T. Blaauw, John S. Brunhaver, Chaitali Chakrabarti, Liangliang Chang, Kuan-Yu Chen, Ming-Hung Chen, Xing Chen, Alex R. Chiriyath, Alhad Daftardar, Ronald G. Dreslinski, Arindam Dutta, Allen-Jasmin Farcas, Yukang Fu, A. Alper Goksoy, Xin He, Md Sahil Hassan, Andrew Herschfelt, Jacob Holtom, Hun-Seok Kim, A. N. Krishnakumar, Yang Li, Owen Ma, Joshua Mack, Saurav Mallik, Sumit K. Mandal, Radu Marculescu, Brittany M. McCall, Trevor N. Mudge, Ümit Y. Ogras, Vishrut Pandey, Saquib Ahmad Siddiqui, Yu-Hsiu Sun, Adarsh A. Venkataramani, Xiangdong Wei, B. R. Willis, Hanguang Yu, Yufan Yue
2022	J	`jnl`	FASCINET: A Fully Automated Single-Board Computer Generator Using Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Morteza Fayazi, Zachary Colter, Zineb Benameur-El Youbi, Javad Bagherzadeh, Tutu Ajayi, Ronald G. Dreslinski
2022	J	`jnl`	Finding and Indexing Vehicle Maneuvers From Dashboard Camera Video. IEEE Trans. Intell. Transp. Syst. Stephen A. Zekany, Thomas F. Larsen, Ronald G. Dreslinski, Thomas F. Wenisch
2022	J	`jnl`	HetSched: Quality-of-Mission Aware Scheduling for Autonomous Vehicle SoCs. CoRR Aporva Amarnath, Subhankar Pal, Hiwot Kassa, Augusto Vega, Alper Buyuktosunoglu, Hubertus Franke, John-David Wellman, Ronald G. Dreslinski, Pradip Bose
2022	C	`conf`	Improving Energy Efficiency of Convolutional Neural Networks on Multi-core Architectures through Run-time Reconfiguration. ISCAS Yan Xiong, Jingtao Li, David T. Blaauw, Hun-Seok Kim, Trevor N. Mudge, Ronald G. Dreslinski, Chaitali Chakrabarti
2022	B	`conf`	Locality-Aware Optimizations for Improving Remote Memory Latency in Multi-GPU Systems. PACT Leul Belayneh, Haojie Ye, Kuan-Yu Chen, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski, Nishil Talati
2022	A*	`conf`	MeNDA: a near-memory multi-way merge solution for sparse transposition and dataflows. ISCA Siying Feng, Xin He, Kuan-Yu Chen, Liu Ke, Xuan Zhang, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski
2022	A*	`conf`	Mint: An Accelerator For Mining Temporal Motifs. MICRO Nishil Talati, Haojie Ye, Sanketh Vedula, Kuan-Yu Chen, Yuhan Chen, Daniel Liu, Yichao Yuan, David T. Blaauw, Alex M. Bronstein, Trevor N. Mudge, Ronald G. Dreslinski
2022	A*	`conf`	NDMiner: accelerating graph pattern mining using near data processing. ISCA Nishil Talati, Haojie Ye, Yichen Yang, Leul Belayneh, Kuan-Yu Chen, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski
2022	J	`jnl`	Power-optimized Deployment of Key-value Stores Using Storage Class Memory. ACM Trans. Storage Hiwot Tadese Kassa, Jason Akers, Mrinmoy Ghosh, Zhichao Cao, Vaibhav Gogte, Ronald G. Dreslinski
2022	A	`conf`	SiC Processors for Extreme High- Temperature Venus Surface Exploration. DATE Heewoo Kim, Javad Bagherzadeh, Ronald G. Dreslinski
2022	B	`conf`	Squaring the circle: Executing Sparse Matrix Computations on FlexTPU - A TPU-Like Processor. PACT Xin He, Kuan-Yu Chen, Siying Feng, Hun-Seok Kim, David T. Blaauw, Ronald G. Dreslinski, Trevor N. Mudge
2022	J	`jnl`	Tablext: A combined neural network and heuristic based table extractor. Array Zach Colter, Morteza Fayazi, Zineb Benameur-El Youbi, Serafina Kamp, Shuyan Yu, Ronald G. Dreslinski
2022	J	`jnl`	Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory. IEEE J. Solid State Circuits Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
2021	—	`conf`	A Deep Dive Into Understanding The Random Walk-Based Temporal Graph Learning. IISWC Nishil Talati, Di Jin, Haojie Ye, Ajay Brahmakshatriya, Ganesh S. Dasika, Saman P. Amarasinghe, Trevor N. Mudge, Danai Koutra, Ronald G. Dreslinski
2021	J	`jnl`	A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors. ACM J. Emerg. Technol. Comput. Syst. Heewoo Kim, Aporva Amarnath, Javad Bagherzadeh, Nishil Talati, Ronald G. Dreslinski
2021	J	`jnl`	An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks. IEEE J. Solid State Circuits Hyochan An, Sam Schiferl, Siddharth Venkatesan, Tim Wesley, Qirui Zhang, Jingcheng Wang, Kyojin Choo, Shiyu Liu, Bowen Liu, Ziyun Li, Luyao Gong, Hengfei Zhong, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim, Dennis Sylvester
2021	J	`jnl`	Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review. IEEE Trans. Circuits Syst. I Regul. Pap. Morteza Fayazi, Zachary Colter, Ehsan Afshari, Ronald G. Dreslinski
2021	J	`jnl`	CHEX-MIX: Combining Homomorphic Encryption with Trusted Execution Environments for Two-party Oblivious Inference in the Cloud. IACR Cryptol. ePrint Arch. Deepika Natarajan, Wei Dai, Ronald G. Dreslinski
2021	A*	`conf`	CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics. DAC Siying Feng, Jiawen Sun, Subhankar Pal, Xin He, Kuba Kaszyk, Dong-Hyeon Park, John Magnus Morton, Trevor N. Mudge, Murray Cole, Michael F. P. O'Boyle, Chaitali Chakrabarti, Ronald G. Dreslinski
2021	J	`jnl`	F1: A Fast and Programmable Accelerator for Fully Homomorphic Encryption (Extended Version). CoRR Axel Feldmann, Nikola Samardzic, Aleksandar Krastev, Srini Devadas, Ronald G. Dreslinski, Karim Eldefrawy, Nicholas Genise, Chris Peikert, Daniel Sánchez
2021	A*	`conf`	F1: A Fast and Programmable Accelerator for Fully Homomorphic Encryption. MICRO Nikola Samardzic, Axel Feldmann, Aleksandar Krastev, Srinivas Devadas, Ronald G. Dreslinski, Christopher Peikert, Daniel Sánchez
2021	A	`conf`	IGOR: Accelerating Byzantine Fault Tolerance for Real-Time Systems with Eager Execution. RTAS Andrew D. Loveless, Ronald G. Dreslinski, Baris Kasikci, Linh Thi Xuan Phan
2021	—	`conf`	Improving Performance of Flash Based Key-Value Stores Using Storage Class Memory as a Volatile Memory Extension. USENIX ATC Hiwot Tadese Kassa, Jason Akers, Mrinmoy Ghosh, Zhichao Cao, Vaibhav Gogte, Ronald G. Dreslinski
2021	A*	`conf`	Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design. HPCA Nishil Talati, Kyle May, Armand Behroozi, Yichen Yang, Kuba Kaszyk, Christos Vasiladiotis, Tarunesh Verma, Lu Li, Brandon Nguyen, Jiawen Sun, John Magnus Morton, Agreen Ahmadi, Todd M. Austin, Michael F. P. O'Boyle, Scott A. Mahlke, Trevor N. Mudge, Ronald G. Dreslinski
2021	A	`conf`	RISC-V Reward: Building Out-of-Order Processors in a Computer Architecture Design Course with an Open-Source ISA. SIGCSE Stephen A. Zekany, Jielun Tan, James A. Connelly, Ronald G. Dreslinski
2021	A*	`conf`	SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator. MICRO Subhankar Pal, Aporva Amarnath, Siying Feng, Michael F. P. O'Boyle, Ronald G. Dreslinski, Christophe Dubach
2021	J	`jnl`	Tablext: A Combined Neural Network And Heuristic Based Table Extractor. CoRR Zach Colter, Morteza Fayazi, Zineb Benameur-El Youbi, Serafina Kamp, Shuyan Yu, Ronald G. Dreslinski
2021	—	`conf`	Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. VLSI Circuits Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
2021	J	`jnl`	Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. CoRR Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
2020	—	`conf`	A 170μW Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge. VLSI Circuits Hyochan An, Siddharth Venkatesan, Sam Schiferl, Tim Wesley, Qirui Zhang, Jingcheng Wang, Kyojin Choo, Shiyu Liu, Bowen Liu, Ziyun Li, Hengfei Zhong, Luyao Gong, David T. Blaauw, Ronald G. Dreslinski, Dennis Sylvester, Hun-Seok Kim
2020	J	`jnl`	A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. IEEE J. Solid State Circuits Dong-Hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Bedford Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski
2020	C	`conf`	Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture. ISCAS Yan Xiong, Jian Zhou, Subhankar Pal, David T. Blaauw, Hun-Seok Kim, Trevor N. Mudge, Ronald G. Dreslinski, Chaitali Chakrabarti
2020	Misc	`conf`	Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture. ICASSP A. Soorishetty, Jian Zhou, Subhankar Pal, David T. Blaauw, H. Kim, Trevor N. Mudge, Ronald G. Dreslinski, Chaitali Chakrabarti
2020	C	`conf`	An Open-source Framework for Autonomous SoC Design with Analog Block Generation. VLSI-SOC Tutu Ajayi, Sumanth Kamineni, Yaswanth K. Cherivirala, Morteza Fayazi, Kyumin Kwon, Mehdi Saligane, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David T. Blaauw, Ronald G. Dreslinski, Benton H. Calhoun, David D. Wentzloff
2020	—	`conf`	CoPTA: Contiguous Pattern Speculating TLB Architecture. SAMOS Yichen Yang, Haojie Ye, Yuhan Chen, Xueyang Liu, Nishil Talati, Xin He, Trevor N. Mudge, Ronald G. Dreslinski
2020	—	`conf`	HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework. IISWC Subhankar Pal, Kuba Kaszyk, Siying Feng, Björn Franke, Murray Cole, Michael F. P. O'Boyle, Trevor N. Mudge, Ronald G. Dreslinski
2020	J	`jnl`	Optimal and Error-Free Multi-Valued Byzantine Consensus Through Parallel Execution. IACR Cryptol. ePrint Arch. Andrew D. Loveless, Ronald G. Dreslinski, Baris Kasikci
2020	B	`conf`	Performance Characterization of Lattice-Based Cryptography Workloads. ISPASS Deepika Natarajan, Ronald G. Dreslinski
2020	A*	`conf`	R2D3: A Reliability Engine for 3D Parallel Systems. DAC Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald G. Dreslinski
2020	J	`jnl`	STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors. CoRR Augusto Vega, Aporva Amarnath, John-David Wellman, Hiwot Kassa, Subhankar Pal, Hubertus Franke, Alper Buyuktosunoglu, Ronald G. Dreslinski, Pradip Bose
2020	A	`conf`	Sparse-TPU: adapting systolic arrays for sparse matrices. ICS Xin He, Subhankar Pal, Aporva Amarnath, Siying Feng, Dong-Hyeon Park, Austin Rovinski, Haojie Ye, Kuan-Yu Chen, Ronald G. Dreslinski, Trevor N. Mudge
2020	J	`jnl`	Tetris: Using Software/Hardware Co-Design to Enable Handheld, Physics-Limited 3D Plane-Wave Ultrasound Imaging. IEEE Trans. Computers Brendan L. West, Jian Zhou, Ronald G. Dreslinski, Oliver D. Kripfgans, J. Brian Fowlkes, Chaitali Chakrabarti, Thomas F. Wenisch
2020	B	`conf`	Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration. PACT Subhankar Pal, Siying Feng, Dong-Hyeon Park, Sung Kim, Aporva Amarnath, Chi-Sheng Yang, Xin He, Jonathan Beaumont, Kyle May, Yan Xiong, Kuba Kaszyk, John Magnus Morton, Jiawen Sun, Michael F. P. O'Boyle, Murray Cole, Chaitali Chakrabarti, David T. Blaauw, Hun-Seok Kim, Trevor N. Mudge, Ronald G. Dreslinski
2019	A	`conf`	3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology. ISLPED Aporva Amarnath, Javad Bagherzadeh, Jielun Tan, Ronald G. Dreslinski
2019	—	`conf`	A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. VLSI Circuits Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski
2019	—	`conf`	A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. VLSI Circuits Subhankar Pal, Dong-Hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael B. Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski
2019	—	`conf`	Classifying Ego-Vehicle Road Maneuvers from Dashcam Video. ITSC Stephen A. Zekany, Ronald G. Dreslinski, Thomas F. Wenisch
2019	B	`conf`	Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective. ISPASS Siying Feng, Subhankar Pal, Yichen Yang, Ronald G. Dreslinski
2019	—	`conf`	SMART: STT-MRAM architecture for smart activation and sensing. MEMSYS Byoungchan Oh, Nilmini Abeyratne, Nam Sung Kim, Ronald G. Dreslinski, Trevor N. Mudge
2019	A*	`conf`	Tetris: A Streaming Accelerator for Physics-Limited 3D Plane-Wave Ultrasound Imaging. DAC Brendan L. West, Jian Zhou, Ronald G. Dreslinski, J. Brian Fowlkes, Oliver Kripfgans, Chaitali Chakrabarti, Thomas F. Wenisch
2018	J	`jnl`	A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles. IEEE J. Solid State Circuits Ziyun Li, Qing Dong, Mehdi Saligane, Benjamin P. Kempke, Luyao Gong, Zhengya Zhang, Ronald G. Dreslinski, Dennis Sylvester, David T. Blaauw, Hun-Seok Kim
2018	—	`conf`	A load balancing technique for memory channels. MEMSYS Byoungchan Oh, Nam Sung Kim, Jeongseob Ahn, Bingchao Li, Ronald G. Dreslinski, Trevor N. Mudge
2018	A*	`conf`	OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator. HPCA Subhankar Pal, Jonathan Beaumont, Dong-Hyeon Park, Aporva Amarnath, Siying Feng, Chaitali Chakrabarti, Hun-Seok Kim, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski
2018	J	`jnl`	The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. IEEE Micro Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, Michael B. Taylor
2017	—	`conf`	14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence. ISSCC Suyoung Bang, Jingcheng Wang, Ziyun Li, Cao Gao, Yejoong Kim, Qing Dong, Yen-Po Chen, Laura Fick, Xun Sun, Ronald G. Dreslinski, Trevor N. Mudge, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester
2017	—	`conf`	3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation. ISSCC Ziyun Li, Qing Dong, Mehdi Saligane, Benjamin P. Kempke, Shijia Yang, Zhengya Zhang, Ronald G. Dreslinski, Dennis Sylvester, David T. Blaauw, Hun-Seok Kim
2017	A	`conf`	A carbon nanotube transistor based RISC-V processor using pass transistor logic. ISLPED Aporva Amarnath, Siying Feng, Subhankar Pal, Tutu Ajayi, Austin Rovinski, Ronald G. Dreslinski
2017	J	`jnl`	Impact of FinFET on Near-Threshold Voltage Scalability. IEEE Des. Test Nathaniel Ross Pinckney, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw, Lucian Shifren, Brian Cline, Saurabh Sinha
2017	J	`jnl`	Reining in Long Tails in Warehouse-Scale Computers with Quick Voltage Boosting Using Adrenaline. ACM Trans. Comput. Syst. Chang-Hong Hsu, Yunqi Zhang, Michael A. Laurenzano, David Meisner, Thomas F. Wenisch, Ronald G. Dreslinski, Jason Mars, Lingjia Tang
2016	A*	`conf`	A low power software-defined-radio baseband processor for the Internet of Things. HPCA Yajing Chen, Shengshuo Lu, Hun-Seok Kim, David T. Blaauw, Ronald G. Dreslinski, Trevor N. Mudge
2016	—	`conf`	Checkpointing Exascale Memory Systems with Existing Memory Technologies. MEMSYS Nilmini Abeyratne, Hsing Min Chen, Byoungchan Oh, Ronald G. Dreslinski, Chaitali Chakrabarti, Trevor N. Mudge
2016	J	`jnl`	Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal Assistant. ACM Trans. Comput. Syst. Johann Hauswald, Michael A. Laurenzano, Yunqi Zhang, Hailong Yang, Yiping Kang, Cheng Li, Austin Rovinski, Arjun Khurana, Ronald G. Dreslinski, Trevor N. Mudge, Vinicius Petrucci, Lingjia Tang, Jason Mars
2016	J	`jnl`	Energy-Autonomous Wireless Communication for Millimeter-Scale Internet-of-Things Sensor Nodes. IEEE J. Sel. Areas Commun. Yajing Chen, Nikolaos Chiotellis, Li-Xuan Chuo, Carl Pfeiffer, Yao Shi, Ronald G. Dreslinski, Anthony Grbic, Trevor N. Mudge, David D. Wentzloff, David T. Blaauw, Hun-Seok Kim
2016	A	`conf`	Enhancing DRAM Self-Refresh for Idle Power Reduction. ISLPED Byoungchan Oh, Nilmini Abeyratne, Jeongseob Ahn, Ronald G. Dreslinski, Trevor N. Mudge
2016	J	`jnl`	Exploring Fine-Grained Heterogeneity with Composite Cores. IEEE Trans. Computers Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke
2016	J	`jnl`	MBus: A System Integration Bus for the Modular Microscale Computing Class. IEEE Micro Pat Pannuto, Yoonmyung Lee, Ye-Sheng Kuo, Zhiyoong Foo, Benjamin P. Kempke, Gyouho Kim, Ronald G. Dreslinski, David T. Blaauw, Prabal Dutta
2016	A*	`conf`	Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability. DAC Nathaniel Ross Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw
2016	J	`jnl`	Sirius Implications for Future Warehouse-Scale Computers. IEEE Micro Johann Hauswald, Michael A. Laurenzano, Yunqi Zhang, Cheng Li, Austin Rovinski, Arjun Khurana, Ronald G. Dreslinski, Trevor N. Mudge, Vinicius Petrucci, Lingjia Tang, Jason Mars
2015	B	`conf`	A study of mobile device utilization. ISPASS Cao Gao, Anthony Gutierrez, Madhav Rajan, Ronald G. Dreslinski, Trevor N. Mudge, Carole-Jean Wu
2015	A*	`conf`	Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting. HPCA Chang-Hong Hsu, Yunqi Zhang, Michael A. Laurenzano, David Meisner, Thomas F. Wenisch, Jason Mars, Lingjia Tang, Ronald G. Dreslinski
2015	A*	`conf`	DjiNN and Tonic: DNN as a service and its implications for future warehouse scale computers. ISCA Johann Hauswald, Yiping Kang, Michael A. Laurenzano, Quan Chen, Cheng Li, Trevor N. Mudge, Ronald G. Dreslinski, Jason Mars, Lingjia Tang
2015	A*	`conf`	MBus: an ultra-low power interconnect bus for next generation nanopower systems. ISCA Pat Pannuto, Yoonmyung Lee, Ye-Sheng Kuo, Zhiyoong Foo, Benjamin P. Kempke, Gyouho Kim, Ronald G. Dreslinski, David T. Blaauw, Prabal Dutta
2015	A*	`conf`	Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers. ASPLOS Johann Hauswald, Michael A. Laurenzano, Yunqi Zhang, Cheng Li, Austin Rovinski, Arjun Khurana, Ronald G. Dreslinski, Trevor N. Mudge, Vinicius Petrucci, Lingjia Tang, Jason Mars
2015	J	`jnl`	Using Graphics Processing Units in an LTE Base Station. J. Signal Process. Syst. Qi Zheng, Yajing Chen, Hyunseok Lee, Ronald G. Dreslinski, Chaitali Chakrabarti, Achilleas Anastasopoulos, Scott A. Mahlke, Trevor N. Mudge
2015	A*	`conf`	WarpPool: sharing requests with inter-warp coalescing for throughput processors. MICRO John Kloosterman, Jonathan Beaumont, Mick Wollman, Ankit Sethia, Ronald G. Dreslinski, Trevor N. Mudge, Scott A. Mahlke
2014	Misc	`conf`	A hybrid approach to offloading mobile image classification. ICASSP Johann Hauswald, Thomas Manville, Q. Zheng, Ronald G. Dreslinski, Chaitali Chakrabarti, Trevor N. Mudge
2014	B	`conf`	A study of Thread Level Parallelism on mobile devices. ISPASS Cao Gao, Anthony Gutierrez, Ronald G. Dreslinski, Trevor N. Mudge, Krisztián Flautner, Geoffrey Blake
2014	—	`conf`	Evaluating private vs. shared last-level caches for energy efficiency in asymmetric multi-cores. ICSAMOS Anthony Gutierrez, Ronald G. Dreslinski, Trevor N. Mudge
2014	B	`conf`	Heterogeneous microarchitectures trump voltage scaling for low-power cores. PACT Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke
2014	A*	`conf`	Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration. MICRO Supreet Jeloka, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, David T. Blaauw
2014	A*	`conf`	Integrated 3D-stacked server designs for increasing physical density of key-value stores. ASPLOS Anthony Gutierrez, Michael Cieslak, Bharan Giridhar, Ronald G. Dreslinski, Luis Ceze, Trevor N. Mudge
2014	A*	`conf`	Quality-of-Service for a High-Radix Switch. DAC Nilmini Abeyratne, Supreet Jeloka, Yiping Kang, David T. Blaauw, Ronald G. Dreslinski, Reetuparna Das, Trevor N. Mudge
2014	B	`conf`	Sources of error in full-system simulation. ISPASS Anthony Gutierrez, Joseph Pusdesris, Ronald G. Dreslinski, Trevor N. Mudge, Chander Sudanthi, Christopher D. Emmons, Mitchell Hayenga, Nigel C. Paver
2014	A*	`conf`	VIX: Virtual Input Crossbar for Efficient Switch Allocation. DAC Supriya Rao, Supreet Jeloka, Reetuparna Das, David T. Blaauw, Ronald G. Dreslinski, Trevor N. Mudge
2013	—	`conf`	Architecting an LTE base station with graphics processing units. SiPS Qi Zheng, Yen-Po Chen, Ronald G. Dreslinski, Chaitali Chakrabarti, Achilleas Anastasopoulos, Scott A. Mahlke, Trevor N. Mudge
2013	A*	`conf`	Catnap: energy proportional multiple network-on-chip. ISCA Reetuparna Das, Satish Narayanasamy, Sudhir Satpathy, Ronald G. Dreslinski
2013	J	`jnl`	Centip3De: A 64-Core, 3D Stacked Near-Threshold System. IEEE Micro Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge
2013	J	`jnl`	Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS. IEEE J. Solid State Circuits David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, David T. Blaauw, Dennis Sylvester
2013	J	`jnl`	Centip3De: a many-core prototype exploring 3D integration and near-threshold computing. Commun. ACM Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge
2013	A	`conf`	Exploring DRAM organizations for energy-efficient and resilient exascale memories. SC Bharan Giridhar, Michael Cieslak, Deepankar Duggal, Ronald G. Dreslinski, Hsing Min Chen, Robert Patti, Betina Hold, Chaitali Chakrabarti, Trevor N. Mudge, David T. Blaauw
2013	A	`conf`	Hardware acceleration for similarity measurement in natural language processing. ISLPED Prateek Tandon, Vahed Qazvinian, Jichuan Chang, Parthasarathy Ranganathan, Ronald G. Dreslinski, Thomas F. Wenisch
2013	J	`jnl`	Limits of Parallelism and Boosting in Dim Silicon. IEEE Micro Nathaniel Ross Pinckney, Ronald G. Dreslinski, Korey Sewell, David Fick, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw
2013	C	`conf`	Parallelization techniques for implementing trellis algorithms on graphics processors. ISCAS Qi Zheng, Yen-Po Chen, Ronald G. Dreslinski, Chaitali Chakrabarti, Achilleas Anastasopoulos, Scott A. Mahlke, Trevor N. Mudge
2013	A*	`conf`	Scaling towards kilo-core processors with asymmetric high-radix topologies. HPCA Nilmini Abeyratne, Reetuparna Das, Qingkun Li, Korey Sewell, Bharan Giridhar, Ronald G. Dreslinski, David T. Blaauw, Trevor N. Mudge
2013	—	`conf`	WiBench: An open source kernel suite for benchmarking wireless systems. IISWC Qi Zheng, Yajing Chen, Ronald G. Dreslinski, Chaitali Chakrabarti, Achilleas Anastasopoulos, Scott A. Mahlke, Trevor N. Mudge
2012	—	`conf`	A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS. ISSCC Sudhir Satpathy, Korey Sewell, Thomas Manville, Yen-Po Chen, Ronald G. Dreslinski, Dennis Sylvester, Trevor N. Mudge, David T. Blaauw
2012	A*	`conf`	Assessing the performance limits of parallelized near-threshold computing. DAC Nathaniel Ross Pinckney, Korey Sewell, Ronald G. Dreslinski, David Fick, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw
2012	—	`conf`	Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores. ISSCC David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw
2012	—	`conf`	Centip3De: A 64-core, 3D stacked, near-threshold system. Hot Chips Symposium Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw
2012	A*	`conf`	Composite Cores: Pushing Heterogeneity Into a Core. MICRO Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke
2012	C	`conf`	Embedded way prediction for last-level caches. ICCD Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch
2012	A*	`conf`	High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service. DAC Sudhir Satpathy, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw
2012	Misc	`conf`	Lazy cache invalidation for self-modifying codes. CASES Anthony Gutierrez, Joseph Pusdesris, Ronald G. Dreslinski, Trevor N. Mudge
2012	A*	`conf`	Process variation in near-threshold wide SIMD architectures. DAC Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Yongjun Park, Chaitali Chakrabarti, Scott A. Mahlke, David T. Blaauw, Trevor N. Mudge
2012	—	`conf`	Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systems. Hot Chips Symposium Ronald G. Dreslinski, Korey Sewell, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas F. Wenisch, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge
2012	J	`jnl`	Swizzle-Switch Networks for Many-Core Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. Korey Sewell, Ronald G. Dreslinski, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas F. Wenisch, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge
2012	B	`conf`	XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems. PACT Ronald G. Dreslinski, Thomas Manville, Korey Sewell, Reetuparna Das, Nathaniel Ross Pinckney, Sudhir Satpathy, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge
2011	A*	`conf`	Bloom Filter Guided Transaction Scheduling. HPCA Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge
2011	—	`conf`	Full-system analysis and characterization of interactive smartphone applications. IISWC Anthony Gutierrez, Ronald G. Dreslinski, Thomas F. Wenisch, Trevor N. Mudge, Ali G. Saidi, Christopher D. Emmons, Nigel C. Paver
2011	A	`conf`	Low power interconnects for SIMD computers. DATE Mark Woh, Sudhir Satpathy, Ronald G. Dreslinski, Danny Kershaw, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge
2011	—	`—`	Near Threshold Computing: From Single Core to Many-Core Energy Efficient Architectures. Ronald G. Dreslinski
2010	A	`conf`	Diet SODA: a power-efficient processor for digital cameras. ISLPED Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Chaitali Chakrabarti, Scott A. Mahlke, Trevor N. Mudge
2010	A*	`conf`	Evolution of thread-level parallelism in desktop applications. ISCA Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge, Krisztián Flautner
2010	J	`jnl`	Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits. Proc. IEEE Ronald G. Dreslinski, Michael Wieckowski, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge
2009	J	`jnl`	A survey of multicore processors. IEEE Signal Process. Mag. Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge
2009	A*	`conf`	Proactive transaction scheduling for contention management. MICRO Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge
2009	—	`conf`	Reconfigurable Multicore Server Processors for Low Power Operation. SAMOS Ronald G. Dreslinski, David Fick, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge
2008	—	`conf`	Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor. SAMOS Emre Özer, Ronald G. Dreslinski, Trevor N. Mudge, Stuart Biles, Krisztián Flautner
2008	A*	`conf`	Reconfigurable energy efficient near threshold cache architectures. MICRO Ronald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David T. Blaauw, Dennis Sylvester, Krisztián Flautner
2007	B	`conf`	An Energy Efficient Parallel Architecture Using Near Threshold Operation. PACT Ronald G. Dreslinski, Bo Zhai, Trevor N. Mudge, David T. Blaauw, Dennis Sylvester
2007	—	`conf`	Analysis of hardware prefetching across virtual page boundaries. Conf. Computing Frontiers Ronald G. Dreslinski, Ali G. Saidi, Trevor N. Mudge, Steven K. Reinhardt
2007	A	`conf`	Energy efficient near-threshold chip multi-processing. ISLPED Bo Zhai, Ronald G. Dreslinski, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester
2006	A*	`conf`	PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor. ASPLOS Taeho Kgil, Shaun D'Souza, Ali G. Saidi, Nathan L. Binkert, Ronald G. Dreslinski, Trevor N. Mudge, Steven K. Reinhardt, Krisztián Flautner
2006	J	`jnl`	The M5 Simulator: Modeling Networked Systems. IEEE Micro Nathan L. Binkert, Ronald G. Dreslinski, Lisa R. Hsu, Kevin T. Lim, Ali G. Saidi, Steven K. Reinhardt
2005	—	`conf`	Performance Analysis of System Overheads in TCP/IP Workloads. IEEE PACT Nathan L. Binkert, Lisa R. Hsu, Ali G. Saidi, Ronald G. Dreslinski, Andrew L. Schultz, Steven K. Reinhardt