Ronald D. Blanton

75 papers A* 3A 33B 1C 2Misc 8Journal 20Unranked 8

Year	Rank	Type	Title / Venue / Authors
2024	Misc	`conf`	Logic-AAA: Debug of Logic Failures with an on-ATE Expert System. VTS Chris Nigh, Ronald D. Blanton
2023	J	`jnl`	Efficient Test Chip Design via Smart Computation. ACM Trans. Design Autom. Electr. Syst. Chenlei Fang, Qicheng Huang, Zeye Liu, Ruizhou Ding, Ronald D. Blanton
2022	A	`conf`	PEPR: Pseudo-Exhaustive Physically-Aware Region Testing. ITC Wei Li, Chris Nigh, Danielle Duvalsaint, Subhasish Mitra, Ronald D. Blanton
2021	A	`conf`	AAA: Automated, On-ATE AI Debug of Scan Chain Failures. ITC Chris Nigh, Gaurav Bhargava, Ronald D. Blanton
2020	J	`jnl`	Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. CoRR Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md. Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks
2020	J	`jnl`	CircuitGraph: A Python package for Boolean circuits. J. Open Source Softw. Joseph Sweeney, Ruben Purdy, Ronald D. Blanton, Lawrence T. Pileggi
2020	B	`conf`	Design Obfuscation versus Test. ETS Farimah Farahmandi, Ozgur Sinanoglu, Ronald D. Blanton, Samuel Pagliarini
2019	—	`conf`	Characterization of Locked Sequential Circuits via ATPG. ITC-Asia Danielle Duvalsaint, Zeye Liu, Ananya Ravikumar, Ronald D. Blanton
2019	J	`jnl`	FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference. CoRR Ruizhou Ding, Zeye Liu, Ting-Wu Chin, Diana Marculescu, Ronald D. Blanton
2019	J	`jnl`	IC Protection Against JTAG-Based Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xuanle Ren, Francisco Pimentel Torres, Ronald D. Blanton, Vítor Grade Tavares
2019	J	`jnl`	On-Chip Diagnosis of Generalized Delay Failures Using Compact Fault Dictionaries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Matthew Layne Beckler, Ronald D. Blanton
2018	C	`conf`	Back-End Layout Reflection for Test Chip Design. ICCD Zeye Liu, Ronald D. Blanton
2018	—	`conf`	CompactNet: High Accuracy Deep Neural Network Optimized for On-Chip Implementation. IEEE BigData Abhinav Goel, Zeye Liu, Ronald D. Blanton
2018	J	`jnl`	Improving Diagnostic Resolution of Failing ICs Through Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yang Xue, Xin Li, Ronald D. Blanton
2017	A	`conf`	Fault simulation acceleration for TRAX dictionary construction using GPUs. ITC Matthew Beckler, Ronald D. Blanton
2017	A	`conf`	Front-end layout reflection for test chip design. ITC Zeye Liu, Phillip Fynan, Ronald D. Blanton
2016	—	`conf`	A Learning-Based Approach to Secure JTAG Against Unseen Scan-Based Attacks. ISVLSI Xuanle Ren, Ronald D. Blanton, Vítor Grade Tavares
2016	A	`conf`	Diagnostic resolution improvement through learning-guided physical failure analysis. ITC Carlston Lim, Yang Xue, Xin Li, Ronald D. Blanton, M. Enamul Amyeen
2015	Misc	`conf`	Efficient built-in self test of regular logic characterization vehicles. VTS Ben Niewenhuis, Ronald D. Blanton
2015	Misc	`conf`	Improving accuracy of on-chip diagnosis via incremental learning. VTS Xuanle Ren, Mitchell Martin, Ronald D. Blanton
2015	Misc	`conf`	Special session: Hot topics: Statistical test methods. VTS Manuel J. Barragán, Gildas Léger, Florence Azaïs, Ronald D. Blanton, Adit D. Singh, Stephen Sunter
2015	A	`conf`	Statistical Learning in Chip (SLIC). ICCAD Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas
2014	A	`conf`	Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling. ITC Shanghang Zhang, Xin Li, Ronald D. Blanton, José Machado da Silva, John M. Carulli Jr., Kenneth M. Butler
2014	A	`conf`	Logic characterization vehicle design for maximal information extraction for yield learning. ITC Ronald D. Blanton, Ben Niewenhuis, Carl Taylor
2014	—	`conf`	SLIC: Statistical learning in chip. ISIC Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas
2013	A	`conf`	DREAMS: DFM rule EvAluation using manufactured silicon. ICCAD Ronald D. Blanton, Fa Wang, Cheng Xue, Pranab K. Nag, Yang Xue, Xin Li
2013	A	`conf`	PADRE: Physically-Aware Diagnostic Resolution Enhancement. ITC Yang Xue, Osei Poku, Xin Li, Ronald D. Blanton
2013	A	`conf`	SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states. ITC Ben Niewenhuis, Ronald D. Blanton, Mudit Bhargava, Ken Mai
2012	J	`jnl`	Improving Diagnosis Through Failing Behavior Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaochun Yu, Ronald D. Blanton
2012	J	`jnl`	Physically-Aware Analysis of Systematic Defects in Integrated Circuits. IEEE Des. Test Comput. Wing Chiu Tam, Ronald D. Blanton
2012	A*	`conf`	Test-data volume optimization for diagnosis. DAC Hongfei Wang, Osei Poku, Xiaochun Yu, Sizhe Liu, Ibrahima Komara, Ronald D. Blanton
2011	J	`jnl`	Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sounil Biswas, Ronald D. Blanton
2011	Misc	`conf`	SLIDER: A fast and accurate defect simulation framework. VTS Wing Chiu Tam, Ronald D. Blanton
2011	J	`jnl`	Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob A. Rutenbar, Ronald D. Blanton
2010	A	`conf`	Automatic classification of bridge defects. ITC Jeffrey E. Nelson, Wing Chiu Tam, Ronald D. Blanton
2010	J	`jnl`	Diagnosis of Integrated Circuits With Multiple Defects of Arbitrary Characteristics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaochun Yu, Ronald D. Blanton
2010	J	`jnl`	Enhancing CMOS Using Nanoelectronic Devices: A Perspective on Hybrid Integrated Systems. Proc. IEEE David S. Ricketts, James A. Bain, Yi Luo, Ronald D. Blanton, Kenneth Mai, Gary K. Fedder
2010	A	`conf`	Estimating defect-type distributions through volume diagnosis and defect behavior attribution. ITC Xiaochun Yu, Ronald D. Blanton
2010	A	`conf`	Systematic defect identification through layout snippet clustering. ITC Wing Chiu Tam, Osei Poku, Ronald D. Blanton
2009	Misc	`conf`	Controlling DPPM through Volume Diagnosis. VTS Xiaochun Yu, Yen-Tzu Lin, Wing Chiu Tam, Osei Poku, Ronald D. Blanton
2009	Misc	`conf`	Maintaining Accuracy of Test Compaction through Adaptive Re-learning. VTS Sounil Biswas, Ronald D. Blanton
2009	Misc	`conf`	Physically-Aware N-Detect Test Relaxation. VTS Yen-Tzu Lin, Chukwuemeka U. Ezekwe, Ronald D. Blanton
2009	A	`conf`	Test effectiveness evaluation through analysis of readily-available tester data. ITC Yen-Tzu Lin, Ronald D. Blanton
2008	A	`conf`	An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation Analysis. ITC Xiaochun Yu, Ronald D. Blanton
2008	A	`conf`	Automated Testability Enhancements for Logic Brick Libraries. DATE Jason G. Brown, Brian Taylor, Ronald D. Blanton, Larry T. Pileggi
2008	A	`conf`	Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon. ITC Yen-Tzu Lin, Osei Poku, Ronald D. Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar
2008	A	`conf`	Improving the Accuracy of Test Compaction through Adaptive Test Update. ITC Sounil Biswas, Ronald D. Blanton
2008	A	`conf`	Physically-Aware N-Detect Test Pattern Selection. DATE Yen-Tzu Lin, Osei Poku, Naresh K. Bhatti, Ronald D. Blanton
2007	A	`conf`	Delay defect diagnosis using segment network faults. ITC Osei Poku, Ronald D. Blanton
2006	A	`conf`	A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior. ITC Rao Desineni, Osei Poku, Ronald D. Blanton
2006	J	`jnl`	Defect Modeling Using Fault Tuples. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ronald D. Blanton, Kumar N. Dwarakanath, Rao Desineni
2006	A	`conf`	Diagnostic Test Generation for Arbitrary Faults. ITC Naresh K. Bhatti, Ronald D. Blanton
2006	J	`jnl`	Statistical Test Compaction Using Binary Decision Trees. IEEE Des. Test Comput. Sounil Biswas, Ronald D. Blanton
2004	—	`conf`	Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST. ISVLSI Chunsheng Liu, Kumar N. Dwarakanath, Krishnendu Chakrabarty, Ronald D. Blanton
2003	J	`jnl`	On the properties of the input pattern fault model. ACM Trans. Design Autom. Electr. Syst. Ronald D. Blanton, John P. Hayes
2002	A	`conf`	Fault Tuples in Diagnosis of Deep-Submicron Circuits. ITC Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels
2002	J	`jnl`	Modeling the Economics of Testing: A DFT Perspective. IEEE Des. Test Comput. Pranab K. Nag, Anne E. Gattiker, Sichao Wei, Ronald D. Blanton, Wojciech Maly
2002	J	`jnl`	Test vector generation for charge sharing failures in dynamic logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton
2001	A*	`conf`	False Coupling Interactions in Static Timing Analysis. DAC Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi
2001	—	`conf`	Relating buffer-oriented microarchitecture validation to high-level pipeline functionality. HLDVT Noppanunt Utamaphethai, Ronald D. Blanton, John Paul Shen
2000	A	`conf`	Analysis of failure sources in surface-micromachined MEMS. ITC Nilmoni Deb, Ronald D. Blanton
2000	A	`conf`	Identification of crosstalk switch failures in domino CMOS circuits. ITC Rahul Kundu, Ronald D. Blanton
2000	J	`jnl`	On the design of fast, easily testable ALU's. IEEE Trans. Very Large Scale Integr. Syst. Ronald D. Blanton, John P. Hayes
2000	A*	`conf`	Universal fault simulation using fault tuples. DAC Kumar N. Dwarakanath, Ronald D. Blanton
2000	A	`conf`	Universal test generation using fault tuples. ITC Rao Desineni, Kumar N. Dwarakanath, Ronald D. Blanton
1999	A	`conf`	Particulate failures for surface-micromachined MEMS. ITC Tao Jiang, Ronald D. Blanton
1998	A	`conf`	Failure modes for stiction in surface-micromachined MEMS. ITC Abhijeet Kolpekwar, Ronald D. Blanton, David Woodilla
1998	A	`conf`	MEMS fault model generation using CARAMEL. ITC Abhijeet Kolpekwar, Chris S. Kellen, Ronald D. Blanton
1997	A	`conf`	Development of a MEMS Testing Methodology. ITC Abhijeet Kolpekwar, Ronald D. Blanton
1997	C	`conf`	Properties of the Input Pattern Fault Model. ICCD Ronald D. Blanton, John P. Hayes
1997	—	`conf`	The input pattern fault model and its application. ED&TC Ronald D. Blanton, John P. Hayes
1997	A	`conf`	To DFT or Not to DFT? ITC Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly
1996	A	`conf`	Synthesis of Self-Testing Finite State Machines from High-Level Specifications. ITC Vishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani
1996	J	`jnl`	Testability of Convergent Tree Circuits. IEEE Trans. Computers Ronald D. Blanton, John P. Hayes
1993	—	`conf`	Efficient Testing of Tree Circuits. FTCS Ronald D. Blanton, John P. Hayes