Ron Kapusta - RankMe

14 papers Journal 6Unranked 8

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A 12b 12GS/s Two-Way Interleaved Pipeline ADC with Integrated Broadband RF VGA in 5nm. ISSCC Haiyang Zhu, Larry Singer, Ron Kapusta, Dan Kelly, Tao Pan, Mike Hensley, Scott Bardsley, Christopher Dillon, Daniel Rey-Losada, Kashif M. Sheikh, Chen-Kai Hsu, Zhao Li, Janet Brunsilius, Enrique Alvarez-Fontecilla, Robert Bishop, Paul Wilkins, Hassan L'Bahy, Adalberto Cantoni, Nuo Zhang, Kaung Myat San Oo, Cihan Asci
2025	—	`conf`	24.8 A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET. ISSCC Junhua Shen, Wei-Hung Chen, Efram Burlingame, Stephen Weinreich, Michael Elliott, Stuart McCracken, Jack Kenney, Janet Brunsilius, Anil Korkmaz, Enrique Alvarez-Fontecilla, Nevena Rakuljic, Ushma Mehta, Ben Sullivan, Jeremy Scuteri, Bac Binh Luu, Mitchell Nichols, Dara Martin, Richard Sullivan, Daniel DeBolt, Ron Kapusta
2025	J	`jnl`	Guest Editorial Introduction to the Special Issue on the 2024 Symposium on VLSI Circuits. IEEE J. Solid State Circuits Ron Kapusta, Sugako Otani
2024	J	`jnl`	Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits. IEEE J. Solid State Circuits Mototsugu Hamada, Ron Kapusta
2018	J	`jnl`	A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS. IEEE J. Solid State Circuits Junhua Shen, Akira Shikata, Lalinda Fernando, Ned Guthrie, Baozhen Chen, Mark Maddox, Nikhil Mascarenhas, Ron Kapusta, Michael C. W. Coln
2016	—	`conf`	A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS. A-SSCC Mark Maddox, Baozhen Chen, Michael C. W. Coln, Ron Kapusta, Junhua Shen, Lalinda Fernando
2015	J	`jnl`	Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. Haiyang Zhu, Ron Kapusta, Yong-Bin Kim
2015	—	`conf`	SAR ADCs in parallel [time-interleaved] converter arrays. CICC Ron Kapusta
2014	J	`jnl`	Sampling Circuits That Break the kT/C Thermal Noise Limit. IEEE J. Solid State Circuits Ron Kapusta, Haiyang Zhu, Colin Lyden
2013	J	`jnl`	A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS. IEEE J. Solid State Circuits Ron Kapusta, Junhua Shen, Steven Decker, Hongxing Li, Eitake Ibaragi, Haiyang Zhu
2013	—	`conf`	A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS. ISSCC Ron Kapusta, Junhua Shen, Steven Decker, Hongxing Li, Eitake Ibaragi
2013	—	`conf`	Sampling circuits that break the kT/C thermal noise limit. CICC Ron Kapusta, Haiyang Zhu, Colin Lyden
2012	—	`conf`	Data converter techniques. CICC Ron Kapusta, Yuji Nakajima
2009	—	`conf`	Nyquist rate ADCs. CICC Eric Naviasky, Ron Kapusta