Román Hermida

103 papers A* 1A 23B 3C 11Misc 3Journal 42Unranked 18

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Reconsidering the performance of DEVS modeling and simulation environments using the DEVStone benchmark. CoRR José L. Risco-Martín, Saurabh Mittal, Juan Carlos Fabero Jiménez, Marina Zapater, Román Hermida
2023	J	`jnl`	Efficient micro data centres deployment for mobile healthcare monitoring systems in IoT urban scenarios. CoRR Kevin Henares, José L. Risco-Martín, José L. Ayala, Román Hermida
2022	J	`jnl`	Efficient micro data centres deployment for mobile healthcare monitoring systems in IoT urban scenarios. J. Simulation Kevin Henares, José L. Risco-Martín, José L. Ayala, Román Hermida
2022	J	`jnl`	Runtime data center temperature prediction using Grammatical Evolution techniques. CoRR Marina Zapater, José L. Risco-Martín, Patricia Arroba, José L. Ayala, José Manuel Moya, Román Hermida
2020	J	`jnl`	Evaluation of blood pressure estimation models based on pulse arrival time. Comput. Electr. Eng. Jose Manuel Bote, Joaquín Recas, Román Hermida
2019	J	`jnl`	A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths. IEEE Trans. Circuits Syst. I Regul. Pap. Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik
2019	J	`jnl`	Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks. IEEE Trans. Computers Min Soo Kim, Alberto A. Del Barrio, Leonardo Tavares Oliveira, Román Hermida, Nader Bagherzadeh
2019	—	`conf`	Modular framework to model critical events in stroke patients. SummerSim Kevin Henares, José L. Risco-Martín, Román Hermida, Gemma Reig Roselló, Román Cárdenas
2018	J	`jnl`	A Modular Low-Complexity ECG Delineation Algorithm for Real-Time Embedded Systems. IEEE J. Biomed. Health Informatics Jose Manuel Bote, Joaquín Recas, Francisco J. Rincón, David Atienza, Román Hermida
2018	J	`jnl`	Complexity reduction in the HEVC/H265 standard based on smooth region classification. Digit. Signal Process. David Guillermo Fernández, Alberto A. Del Barrio, Guillermo Botella Juan, Carlos García, Manuel Prieto, Román Hermida
2018	—	`conf`	Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks. ASP-DAC Min Soo Kim, Alberto A. Del Barrio, Román Hermida, Nader Bagherzadeh
2017	A	`conf`	A slack-based approach to efficiently deploy radix 8 booth multipliers. DATE Alberto A. Del Barrio, Román Hermida
2017	J	`jnl`	Reconsidering the performance of DEVS modeling and simulation environments using the DEVStone benchmark. Simul. José L. Risco-Martín, Saurabh Mittal, Juan Carlos Fabero Jiménez, Marina Zapater, Román Hermida
2016	J	`jnl`	A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alberto A. Del Barrio, Jason Cong, Román Hermida
2016	J	`jnl`	A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier. IEEE Trans. Computers Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik
2016	J	`jnl`	Runtime data center temperature prediction using Grammatical Evolution techniques. Appl. Soft Comput. Marina Zapater, José L. Risco-Martín, Patricia Arroba, José L. Ayala, José Manuel Moya, Román Hermida
2014	J	`jnl`	Generic Markov model of the contention access period of IEEE 802.15.4 MAC layer. Digit. Signal Process. Joaquín Recas, Nadia Khaled, Alberto A. Del Barrio, Román Hermida
2014	J	`jnl`	Improving circuit performance with multispeculative additive trees in high-level synthesis. Microelectron. J. Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, Jose Manuel Mendias, María C. Molina
2014	J	`jnl`	Ultra-low-power adder stage design for exascale floating point units. ACM Trans. Embed. Comput. Syst. Alberto A. Del Barrio, Nader Bagherzadeh, Román Hermida
2013	J	`jnl`	A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths. Integr. Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida
2013	C	`conf`	Exploring the energy efficiency of Multispeculative Adders. ICCD Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik
2013	J	`jnl`	Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials. Integr. José Luis Imaña, Román Hermida, Francisco Tirado
2013	A	`conf`	Multispeculative additive trees in high-level synthesis. DATE Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, Jose Manuel Mendias, María C. Molina
2012	J	`jnl`	Multispeculative Addition Applied to Datapath Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, José M. Mendías, María C. Molina
2011	J	`jnl`	A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, Jose Manuel Mendias, Román Hermida
2011	A	`conf`	Power optimization in heterogenous datapaths. DATE Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida
2010	A	`conf`	Using Speculative Functional Units in high level synthesis. DATE Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Román Hermida, Seda Ogrenci Memik
2009	J	`jnl`	A framework for low energy data management in reconfigurable multi-context architectures. J. Syst. Archit. Marcos Sánchez-Élez, Nader Bagherzadeh, Román Hermida
2009	J	`jnl`	Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. María C. Molina, Rafael Ruiz-Sautua, Pedro Garcia-Repetto, Román Hermida
2008	C	`conf`	Applying speculation techniques to implement functional units. ICCD Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida, Francisco Tirado
2008	C	`conf`	Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis. DSD Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida
2008	J	`jnl`	Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures. IET Comput. Digit. Tech. Fredy Rivera, Marcos Sánchez-Élez, Román Hermida, Nader Bagherzadeh
2007	A	`conf`	Area optimization of multi-cycle operators in high-level synthesis. DATE María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida
2007	J	`jnl`	Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis CoRR Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
2007	J	`jnl`	HW-SW emulation framework for temperature-aware design in MPSoCs. ACM Trans. Design Autom. Electr. Syst. David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida
2006	J	`jnl`	Bitwise scheduling to balance the computational cost of behavioral specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida
2006	B	`conf`	Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures. FPL Fredy Rivera, Marcos Sánchez-Élez, Milagros Fernández, Román Hermida, Nader Bagherzadeh
2006	J	`jnl`	Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials. IEEE Trans. Very Large Scale Integr. Syst. José Luis Imaña, Román Hermida, Francisco Tirado
2006	A	`conf`	Pre-synthesis optimization of multiplications to improve circuit performance. DATE Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
2005	A	`conf`	A Complete Network-On-Chip Emulation Framework. DATE Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor
2005	—	`conf`	A novel approach for network on chip emulation. ISCAS (3) Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor
2005	—	`conf`	Arrival time aware scheduling to minimize clock cycle length. ASP-DAC Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
2005	A	`conf`	Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. DATE Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
2005	A	`conf`	Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures. IPDPS Fredy Rivera, Marcos Sánchez-Élez, Milagros Fernández, Román Hermida, Nader Bagherzadeh
2005	A	`conf`	Performance-driven read-after-write dependencies softening in high-level synthesis. ICCAD Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias, Román Hermida
2005	—	`conf`	Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs. PARCO J. B. Pérez-Ramas, David Atienza, Miguel Peón-Quirós, Ivan Magan, Jose Manuel Mendias, Román Hermida
2004	J	`jnl`	Annealing placement by thermodynamic combinatorial optimization. ACM Trans. Design Autom. Electr. Syst. Juan de Vicente, Juan Lanchares, Román Hermida
2004	A	`conf`	Behavioural Bitwise Scheduling Based on Computational Effort Balancing. DATE María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
2004	—	`conf`	Behavioural Scheduling to Balance the Bit-Level Computational Effort. ISVLSI María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
2004	Misc	`conf`	Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures. CODES+ISSS Fredy Rivera, Marcos Sánchez-Élez, Milagros Fernández, Román Hermida, Nader Bagherzadeh
2004	C	`conf`	Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. PDP José Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
2003	J	`jnl`	Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources. J. Syst. Archit. María C. Molina, José M. Mendías, Román Hermida
2003	—	`conf`	Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. PATMOS María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
2003	A	`conf`	High-Level Allocation to Minimize Internal Hardware Wastage. DATE María C. Molina, José M. Mendías, Román Hermida
2003	A	`conf`	Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures. DATE Marcos Sánchez-Élez, Milagros Fernández, Manuel L. Anido, Haitao Du, Nader Bagherzadeh, Román Hermida
2003	A	`conf`	Multi-FPGA Systems Synthesis by Means of Evolutionary Computation. GECCO José Ignacio Hidalgo, Francisco Fernández, Juan Lanchares, Juan Manuel Sánchez-Pérez, Román Hermida, Marco Tomassini, Ranieri Baraglia, Raffaele Perego, Oscar Garnica
2003	—	`conf`	Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. PATMOS Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
2002	A	`conf`	A Complete Data Scheduler for Multi-Context Reconfigurable Architectures. DATE Marcos Sánchez-Élez, Milagros Fernández, Rafael Maestre, Román Hermida, Nader Bagherzadeh, Fadi J. Kurdahi
2002	C	`conf`	A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design. DSD José Ignacio Hidalgo, Juan Lanchares, Aitor Ibarra, Román Hermida
2002	—	`conf`	A New Methodology to Design Low-Power Asynchronous Circuits. PATMOS Oscar Garnica, Juan Lanchares, Román Hermida
2002	J	`jnl`	A global approach to improve conditional hardware reuse in high-level synthesis. J. Syst. Archit. Olga Peñalba, José M. Mendías, Román Hermida
2002	J	`jnl`	A study about the efficiency of formal high-level synthesis applied to verification. Integr. José M. Mendías, Román Hermida, Olga Peñalba
2002	C	`conf`	Bit-Level Allocation of Multiple-Precision Specifications. DSD María C. Molina, José M. Mendías, Román Hermida
2002	A	`conf`	Bit-level scheduling of heterogeneous behavioural specifications. ICCAD María C. Molina, José M. Mendías, Román Hermida
2002	C	`conf`	Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis. DSD José M. Mendías, Román Hermida, María C. Molina, Olga Peñalba
2002	A	`conf`	FPGA Placement by Thermodynamic Combinatorial Optimization. DATE Juan de Vicente, Juan Lanchares, Román Hermida
2002	A*	`conf`	High-level synthesis of multiple-precision circuitsindependent of data-objects length. DAC María C. Molina, José M. Mendías, Román Hermida
2002	A	`conf`	Maximizing Conditonal Reuse by Pre-Synthesis Transformations. DATE Olga Peñalba, José M. Mendías, Román Hermida
2002	A	`conf`	Multiple-Precision Circuits Allocation Independent of Data-Objects Length. DATE María C. Molina, José M. Mendías, Román Hermida
2002	J	`jnl`	Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. Fundam. Informaticae Oscar Garnica, Juan Lanchares, Román Hermida
2002	C	`conf`	Optimization of Equational Specifications Using Genetic Techniques. DSD Aitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida
2002	C	`conf`	Source Code Transformation to Improve Conditional Hardware Reuse. DSD Olga Peñalba, José M. Mendías, Román Hermida
2002	B	`conf`	Transformation of Equational Specification by Means of Genetic Programming. EuroGP Aitor Ibarra, Juan Lanchares, Jose Manuel Mendias, José Ignacio Hidalgo, Román Hermida
2001	—	`conf`	A data scheduler for multi-context reconfigurable architectures. ISSS Marcos Sánchez-Élez, Milagros Fernández, Román Hermida, Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh
2001	J	`jnl`	A formal approach to context scheduling for multicontext reconfigurable architectures. IEEE Trans. Very Large Scale Integr. Syst. Rafael Maestre, F. Kurdahl, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh
2001	J	`jnl`	A framework for reconfigurable computing: task scheduling and context management. IEEE Trans. Very Large Scale Integr. Syst. Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh
2001	A	`conf`	A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits. DATE Oscar Garnica, Juan Lanchares, Román Hermida
2001	J	`jnl`	Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing. J. Syst. Archit. Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh
2001	—	`conf`	Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. ACSD Oscar Garnica, Juan Lanchares, Román Hermida
2001	—	`ed.`	Proceedings of the 14th International Symposium on Systems Synthesis, ISSS 2001, Montrél, Québec, Canada, September 30 - October 3, 2001. ISSS Román Hermida, El Mostapha Aboulhamid
2000	C	`conf`	Adaptive FPGA Placement by Natural Optimization. IEEE International Workshop on Rapid System Prototyping Juan de Vicente, Juan Lanchares, Román Hermida
2000	Misc	`conf`	Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. FCCM Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh
2000	C	`conf`	Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. ICCD Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh
2000	—	`conf`	Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms. EUROMICRO José Ignacio Hidalgo, Juan Lanchares, Román Hermida
2000	—	`ed.`	Proceedings of the 13th International Symposium on System Synthesis, ISSS'00, Madrid, Spain, September 20-22, 2000. ISSS Fadi J. Kurdahi, Román Hermida
1999	—	`conf`	A Framework for Scheduling and Context Allocation in Reconfigurable Computing. ISSS Rafael Maestre, Milagros Fernández, Román Hermida, Nader Bagherzadeh
1999	—	`conf`	A Unified Algorithm for Mutual Exclusiveness Identification. EUROMICRO Olga Peñalba, José M. Mendías, Román Hermida
1999	A	`conf`	Kernel Scheduling in Reconfigurable Computing. DATE Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh, Román Hermida, Milagros Fernández
1999	B	`conf`	Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies. FPL Juan de Vicente, Juan Lanchares, Román Hermida
1999	A	`conf`	The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach. DATE Juan Antonio Maestro, Daniel Mozos, Román Hermida
1998	A	`conf`	Correct High-Level Synthesis: a Formal Perspective. DATE José M. Mendías, Román Hermida
1998	—	`conf`	RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing. EUROMICRO Juan de Vicente, Juan Lanchares, Román Hermida
1997	J	`jnl`	A unified approach for scheduling and allocation. Integr. R. Moreno, Román Hermida, Milagros Fernández, Hortensia Mecha
1997	Misc	`conf`	Formal Techniques for Hardware Allocation. VLSI Design José M. Mendías, Román Hermida, Milagros Fernández
1996	—	`conf`	Algebraic Support for Transformational Hardware Allocation. ED&TC José M. Mendías, Román Hermida, Milagros Fernández
1996	J	`jnl`	Register estimation in unscheduled dataflow graphs. ACM Trans. Design Autom. Electr. Syst. R. Moreno, Román Hermida, Milagros Fernández
1994	J	`jnl`	Clock cycle estimation based on dead time and control unit area minimization. Microprocess. Microprogramming Hortensia Mecha, Milagros Fernández, Román Hermida, Daniel Mozos, Katzalin Olcoz
1993	—	`conf`	An approach to module binding by fuzzy partitioning. EURO-DAC Román Hermida, Milagros Fernández, Francisco Tirado, Victor Manuel Sanchez, Pablo Ruperez
1993	J	`jnl`	Global hardware synthesis guided by realistic probability computation. Microprocess. Microprogramming R. Moreno, Román Hermida, Daniel Mozos, Katzalin Olcoz
1992	J	`jnl`	Design control in a high level synthesis system. Microprocess. Microprogramming Daniel Mozos, Julio Septién, Francisco Tirado, Román Hermida
1992	—	`conf`	Heuristics for branch-and-bound global allocation. EURO-DAC Julio Septién, Daniel Mozos, Francisco Tirado, Román Hermida, Milagros Fernández
1991	J	`jnl`	A hardware allocator guided by cost functions. Microprocessing and Microprogramming J. Septiéna, Daniel Mozos, Román Hermida, Francisco Tirado
1990	J	`jnl`	An approach to minimal-time scheduling of micro-operations. Microprocessing and Microprogramming Alfonso Sotelo, Julio Septién, Román Hermida, Milagros Fernández