Romesh Kumar Nandwana

27 papers Journal 12Unranked 14

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	A 7 pA/$\surd\text{Hz}$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS. ISSCC Kadaba Lakshmikumar, Alexander Kurylak, Romesh Kumar Nandwana, Bibhu Das, Joe Pampanin, Mike Brubaker, Pavan Kumar Hanumolu
2022	J	`jnl`	An Interference Suppression Technique for Millimeter-Wave LC VCOs Using a Multiport Coupled Inductor. IEEE Trans. Circuits Syst. II Express Briefs Abhishek Bhat, Romesh Kumar Nandwana, Kadaba Lakshmikumar
2022	—	`conf`	High-Performance CMOS TIA for Data Center Optical Interconnects. BCICTS Kadaba R. Lakshmikumar, Alexander Kurylak, Romesh Kumar Nandwana, Bibhu Das, Joe Pampanin, Vito Boccuzzi, Pavan Kumar Hanumolu
2021	J	`jnl`	A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling. IEEE J. Solid State Circuits Mostafa Gamal Ahmed, Dongwook Kim, Romesh Kumar Nandwana, Ahmed Elkholy, Kadaba R. Lakshmikumar, Pavan Kumar Hanumolu
2019	J	`jnl`	A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler. IEEE J. Solid State Circuits Ahmed Elkholy, Daniel Coombs, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu
2019	J	`jnl`	A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links. IEEE J. Solid State Circuits Kadaba Lakshmikumar, Alexander Kurylak, Manohar Nagaraju, Richard Booth, Romesh Kumar Nandwana, Joe Pampanin, Vito Boccuzzi
2017	—	`conf`	29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. ISSCC Romesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu
2017	—	`conf`	8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS. ISSCC Daniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu
2017	J	`jnl`	A 0.0021 mm IEEE J. Solid State Circuits Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu
2017	—	`conf`	A 0.7V time-based inductor for fully integrated low bandwidth filter applications. CICC Braedon Salz, Mrunmay Talegaonkar, Guanghua Shu, Ahmed Elmallah, Romesh Kumar Nandwana, Bibhudatta Sahoo, Pavan Kumar Hanumolu
2017	J	`jnl`	A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC. IEEE Trans. Circuits Syst. I Regul. Pap. Romesh Kumar Nandwana, Saurabh Saxena, Amr Elshazly, Kartikeya Mayaram, Pavan Kumar Hanumolu
2017	J	`jnl`	A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. IEEE J. Solid State Circuits Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Pavan Kumar Hanumolu
2017	—	`conf`	A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS. CICC Junheng Zhu, Makrand Mahalley, Guanghua Shu, Woo-Seok Choi, Romesh Kumar Nandwana, Ahmed Elkholy, Bibhudatta Sahoo, Pavan Kumar Hanumolu
2017	J	`jnl`	A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
2017	—	`—`	Clock multiplication techniques for high-speed I/Os Romesh Kumar Nandwana
2016	—	`conf`	19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS. ISSCC Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu
2016	—	`conf`	23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. ISSCC Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu
2016	J	`jnl`	A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider. IEEE J. Solid State Circuits Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu
2015	—	`conf`	12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm ISSCC Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Ahmad Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu
2015	—	`conf`	A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. VLSIC Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu
2015	J	`jnl`	A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator. IEEE J. Solid State Circuits Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu
2015	—	`conf`	A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter. CICC Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu
2015	J	`jnl`	A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. IEEE J. Solid State Circuits Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2014	—	`conf`	A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. VLSIC Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
2014	—	`conf`	A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
2014	J	`jnl`	A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis. IEEE J. Solid State Circuits Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu
2013	—	`conf`	A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter. CICC Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu