Roman L. Lysecky

58 papers A* 5A 9B 2C 1Misc 6Journal 21Unranked 14
YearRankTypeTitle / Venue / Authors
2016 B conf
Model-Driven Optimization of Data-Adaptable Embedded Systems.
COMPSAC
Adrian Lizarraga, Roman L. Lysecky, Jonathan Sprinkle
2015 J jnl
Application-Specific Customization of Dynamic Profiling Mechanisms for Sensor Networks.
IEEE Access
Lu Ding, Adrian Lizarraga, Ashish Shenoy, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky
2015 J jnl
Security challenges for medical devices.
Commun. ACM
Johannes Sametinger, Jerzy W. Rozenblit, Roman L. Lysecky, Peter Ott
2015 C conf
Students learn more with less text that covers the same core topics.
FIE
Alex D. Edgcomb, Frank Vahid, Roman L. Lysecky
2015 J jnl
System-Level Observation Framework for Non-Intrusive Runtime Monitoring of Embedded Systems.
ACM Trans. Design Autom. Electr. Syst.
Jong Chul Lee, Roman L. Lysecky
2014 J jnl
Workload assignment considering NBTI degradation in multicore systems.
ACM J. Emerg. Technol. Comput. Syst.
Jin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Roveda
2013 — conf
How You Can Learn to Stop Worrying and Love Reconfigurable Embedded Systems: A Tutorial.
ECBS
Nathan Sandoval, Casey Mackin, Roman L. Lysecky, Jonathan Sprinkle
2013 J jnl
Profiling and online system-level performance and power estimation for dynamically adaptable embedded systems.
ACM Trans. Embed. Comput. Syst.
Jingqing Mu, Karthik Shankar, Roman L. Lysecky
2013 — conf
Runtime hardware/software task transition scheduling for data-adaptable embedded systems.
FPT
Nathan Sandoval, Casey Mackin, Sean Whitsitt, Roman L. Lysecky, Jonathan Sprinkle
2013 — conf
System Throughput Optimization and Runtime Communication Middleware Supporting Dynamic Software-Hardware Task Migration in Data Adaptable Embedded Systems.
ECBS
Nathan Sandoval, Casey Mackin, Sean Whitsitt, Roman L. Lysecky, Jonathan Sprinkle
2012 J jnl
A self-tuning design methodology for power-efficient multi-core systems.
ACM Trans. Design Autom. Electr. Syst.
Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda
2012 Misc conf
Adaptive online heuristic performance estimation and power optimization for reconfigurable embedded systems.
CODES+ISSS
Jingqing Mu, Roman L. Lysecky
2012 — conf
An overseer control methodology for data adaptable embedded systems.
MPM@MoDELS
Sean Whitsitt, Jonathan Sprinkle, Roman L. Lysecky
2012 — conf
Automated Software Generation and Hardware Coprocessor Synthesis for Data-Adaptable Reconfigurable Systems.
ECBS
Andrew Milakovich, Vijay Shankar Gopinath, Roman L. Lysecky, Jonathan Sprinkle
2012 — conf
Online algorithms for wireless sensor networks dynamic optimization.
CCNC
Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky
2011 J jnl
Efficient hardware-based nonintrusive dynamic application profiling.
ACM Trans. Embed. Comput. Syst.
Ajay Nair, Karthik Shankar, Roman L. Lysecky
2011 — conf
Hardware/Software Communication Middleware for Data Adaptable Embedded Systems.
ECBS
Sachidanand Mahadevan, Vijay Shankar Gopinath, Roman L. Lysecky, Jonathan Sprinkle, Jerzy W. Rozenblit, Michael W. Marcellin
2011 — conf
Modeling of Data Adaptable Reconfigurable Embedded Systems.
ECBS
Vijay Shankar Gopinath, Jonathan Sprinkle, Roman L. Lysecky
2011 — conf
Profile assisted online system-level performance and power estimation for dynamic reconfigurable embedded systems.
ASP-DAC
Jingqing Mu, Roman L. Lysecky
2010 B conf
A lightweight dynamic optimization methodology for wireless sensor networks.
WiMob
Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky
2010 A conf
A self-evolving design methodology for power efficient multi-core systems.
ICCAD
Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda
2010 J jnl
Configuration Locking and Schedulability Estimation for Reduced Reconfiguration Overheads of Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Rahul Kalra, Roman L. Lysecky
2010 J jnl
Control Focused Soft Error Detection for Embedded Applications.
IEEE Embed. Syst. Lett.
Karthik Shankar, Roman L. Lysecky
2010 J jnl
Evaluation of Dynamic Profiling Methodologies for Optimization of Sensor Networks.
IEEE Embed. Syst. Lett.
Ashish Shenoy, Jeff Hiner, Susan Lysecky, Roman L. Lysecky, Ann Gordon-Ross
2010 — conf
Transaction-Level Modeling for Sensor Networks Using SystemC.
SUTC/UMC
Jeff Hiner, Ashish Shenoy, Roman L. Lysecky, Susan Lysecky, Ann Gordon-Ross
2010 — conf
Workload capacity considering NBTI degradation in multi-core systems.
ASP-DAC
Jin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang
2009 J jnl
Autonomous hardware/software partitioning and voltage/frequency scaling for low-power embedded systems.
ACM Trans. Design Autom. Electr. Syst.
Jingqing Mu, Roman L. Lysecky
2009 J jnl
Design and implementation of a MicroBlaze-based warp processor.
ACM Trans. Embed. Comput. Syst.
Roman L. Lysecky, Frank Vahid
2009 J jnl
Float-to-fixed and fixed-to-float hardware converters for rapid hardware/software partitioning of floating point software applications to static and dynamic fixed point coprocessors.
Des. Autom. Embed. Syst.
Lance Saldanha, Roman L. Lysecky
2009 A* conf
Non-intrusive dynamic application profiling for multitasked applications.
DAC
Karthik Shankar, Roman L. Lysecky
2008 — conf
Design space exploration for application specific FPGAS in system-on-a-chip designs.
SoCC
Mark Hammerquist, Roman L. Lysecky
2008 Misc conf
Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits.
CODES+ISSS
Lance Saldanha, Roman L. Lysecky
2008 Misc conf
Non-intrusive dynamic application profiler for detailed loop execution characterization.
CASES
Ajay Nair, Roman L. Lysecky
2008 J jnl
Scalability and Parallel Execution of Warp Processing: Dynamic Hardware/Software Partitioning.
Int. J. Parallel Program.
Roman L. Lysecky
2008 J jnl
Warp Processing: Dynamic Translation of Binaries to FPGA Circuits.
Computer
Frank Vahid, Greg Stitt, Roman L. Lysecky
2007 J jnl
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning
CoRR
Roman L. Lysecky, Frank Vahid
2007 A conf
Low-power warp processor for power efficient high-performance embedded systems.
DATE
Roman L. Lysecky
2006 A conf
Application-specific customization of parameterized FPGA soft-core processors.
ICCAD
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen
2006 A conf
Conjoining soft-core FPGA processors.
ICCAD
David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky
2006 J jnl
Warp Processors.
ACM Trans. Design Autom. Electr. Syst.
Roman L. Lysecky, Greg Stitt, Frank Vahid
2005 Misc conf
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation.
FCCM
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
2005 A conf
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning.
DATE
Roman L. Lysecky, Frank Vahid
2005 A conf
Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only).
FPGA
Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers
2004 A conf
A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning.
DATE
Roman L. Lysecky, Frank Vahid
2004 A conf
A Self-Tuning Cache Architecture for Embedded Systems.
DATE
Chuanjun Zhang, Frank Vahid, Roman L. Lysecky
2004 J jnl
A fast on-chip profiler memory using a pipelined binary tree.
IEEE Trans. Very Large Scale Integr. Syst.
Roman L. Lysecky, Susan Cotterell, Frank Vahid
2004 J jnl
A self-tuning cache architecture for embedded systems.
ACM Trans. Embed. Comput. Syst.
Chuanjun Zhang, Frank Vahid, Roman L. Lysecky
2004 A* conf
Dynamic FPGA routing for just-in-time FPGA compilation.
DAC
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
2003 Misc conf
A codesigned on-chip logic minimizer.
CODES+ISSS
Roman L. Lysecky, Frank Vahid
2003 A* conf
Dynamic hardware/software partitioning: a first approach.
DAC
Greg Stitt, Roman L. Lysecky, Frank Vahid
2003 J jnl
Highly configurable platforms for embedded computing systems.
Microelectron. J.
Frank Vahid, Roman L. Lysecky, Chuanjun Zhang, Greg Stitt
2003 A* conf
On-chip logic minimization.
DAC
Roman L. Lysecky, Frank Vahid
2002 A* conf
A fast on-chip profiler memory.
DAC
Roman L. Lysecky, Susan Cotterell, Frank Vahid
2002 J jnl
Prefetching for improved bus wrapper performance in cores.
ACM Trans. Design Autom. Electr. Syst.
Roman L. Lysecky, Frank Vahid
2000 Misc conf
A first-step towards an architecture tuning methodology for low power.
CASES
Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky
2000 — conf
Experiments with the Peripheral Virtual Component Interface.
ISSS
Roman L. Lysecky, Frank Vahid, Tony Givargis
2000 A conf
Techniques for Reducing Read Latency of Core Bus Wrappers.
DATE
Roman L. Lysecky, Frank Vahid, Tony Givargis
1999 — conf
Pre-Fetching for Improved Core Interfacing.
ISSS
Roman L. Lysecky, Frank Vahid, Rilesh Patel, Tony Givargis