Rolf Drechsler

1031 papers A* 26A 114B 36C 190Misc 29Journal 207Unranked 397

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Advanced And-Inverter Graph Decomposition Technique for Reducing Circuit Complexity. ACM Trans. Design Autom. Electr. Syst. Mohamed A. Nadeem, Luca Müller, Chandan Kumar Jha, Rolf Drechsler
2026	Misc	`conf`	DIVIAC: Library of Input Data Aware Approximate Dividers with Partial Exact Minimization. VLSID Chandan Kumar Jha, Sallar Ahmadi-Pour, Sajjad Parvin, Rolf Drechsler
2026	J	`jnl`	Efficient Evolution of Variable Ordering for Binary Decision Diagram Optimization. IEEE Trans. Evol. Comput. Rune Krauss, Rolf Drechsler
2026	J	`jnl`	Formally Verifying Multiply-and-Accumulate Architectures Using Symbolic Computer Algebra. SN Comput. Sci. Lennart Weingarten, Kamalika Datta, Rolf Drechsler
2026	J	`jnl`	Late Breaking Results: Conversion of Neural Networks into Logic Flows for Edge Computing. CoRR Daniel Stein, Shaoyi Huang, Rolf Drechsler, Bing Li, Grace Li Zhang
2026	Misc	`conf`	PolyEMAC: Polynomial Error Metrics Analysis in Approximate Computing. VLSID Mohamed A. Nadeem, Chandan Kumar Jha, Rolf Drechsler
2026	J	`jnl`	veriSiM: Formal Verification of SPICE Netlists for MAGIC-Based Logic-in-Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chandan Kumar Jha, Simranjeet Singh, Khushboo Qayyum, Ankit Bende, Muhammad Hassan, Vikas Rana, Farhad Merchant, Rolf Drechsler
2025	C	`conf`	A Comprehensive Synthesis and Verification Approach for RRAM-Based Neuromorphic Computing. DSD Fatemeh Shirinzadeh, Abhoy Kole, Kamalika Datta, Saeideh Shirinzadeh, Rolf Drechsler
2025	A	`conf`	Accurate and Extensible Symbolic Execution of Binary Code Based on Formal ISA Semantics. DATE Sören Tempel, Tobias Brandt, Christoph Lüth, Christian Dietrich, Rolf Drechsler
2025	J	`jnl`	Auto-OPS: A Framework for Automated Optical Probing Simulation on GDS-II. IEEE Embed. Syst. Lett. Paul Flammarion, Sajjad Parvin, Frank Sill Torres, Rolf Drechsler
2025	C	`conf`	Automatic Polynomial Formal Verification of a Floating-Point Multiplier. DSD Jan Kleinekathöfer, Rolf Drechsler
2025	C	`conf`	BDD Meets SAT: Binary Hybrid Diagrams for Efficient Generation of Multiple Solutions. FDL Rune Krauss, Luca Müller, Marius Marach, Rolf Drechsler
2025	J	`jnl`	Comparing Methods for the Cross-Level Verification of SystemC Peripherals with Symbolic Execution. CoRR Karl Aaron Rudkowski, Sallar Ahmadi-Pour, Rolf Drechsler
2025	J	`jnl`	Correct and Verify - CAV: Exploiting Binary Decision Diagrams to Enable Formal Verification of Approximate Adders With Correct Carry Bits. IEEE Trans. Circuits Syst. I Regul. Pap. Chandan Kumar Jha, Khushboo Qayyum, Muhammad Hassan, Rolf Drechsler
2025	A	`conf`	CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design. DATE Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li
2025	C	`conf`	CrosSym: Cross-Level Verification of SystemC Peripherals using Symbolic Execution. DDECS Karl Aaron Rudkowski, Sallar Ahmadi-Pour, Rolf Drechsler
2025	—	`conf`	Data-/ Digital-Science-Community Workshop 2025: Entwicklungen, Synergien und nächste Schritte. INFORMATIK Lena Steinmann, Helen Pfuhl, Dirk Nowotka, Rolf Drechsler
2025	—	`conf`	Daten als Brücke: Interdisziplinäre Zusammenarbeit zwischen Digital Humanities und Data Science im Projekt DataNord. DHd Nele Fuchs, Lena Steinmann, Rolf Drechsler
2025	—	`conf`	Daten als Brücke: Interdisziplinäre Zusammenarbeit zwischen Digital Humanities und Data Science im Projekt DataNord. DHd Nele Fuchs, Lena Steinmann, Rolf Drechsler
2025	J	`jnl`	Divider verification using symbolic computer algebra and delayed don't care optimization: theory and practical implementation. Formal Methods Syst. Des. Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler
2025	B	`conf`	European Test Symposium Teams: an Anniversary Snapshot. ETS Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2025	Misc	`conf`	FARAD: Automated Formal Verification of Approximate Restoring Array Dividers. VLSID Chandan Kumar Jha, Khushboo Qayyum, Muhammad Hassan, Rolf Drechsler
2025	J	`jnl`	FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits. ACM Trans. Design Autom. Electr. Syst. Sallar Ahmadi-Pour, Sajjad Parvin, Chandan Kumar Jha, Rolf Drechsler
2025	—	`conf`	Fast and Scalable MAGIC-Based Wallace Tree Multiplier for In-Memory Computing. CCMCC Saeideh Nabipour, Kamalika Datta, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler
2025	C	`conf`	ForMAt: Formal Verification of Scalable Multiply and Accumulate Units. FDL Lennart Weingarten, Kamalika Datta, Rolf Drechsler
2025	—	`conf`	Formal Verification of Error Bounds for Resistive-Switching-Based Multilevel Matrix-Vector Multipliers. ISQED Kemal Çaglar Coskun, Chandan Kumar Jha, Muhammad Hassan, Rolf Drechsler
2025	A	`conf`	FrEDDY: Modular and Efficient Framework to Engineer Decision Diagrams Yourself. DATE Rune Krauss, Jan Zielasko, Rolf Drechsler
2025	—	`conf`	Interactive Visualization with the R Package Shiny: A Tool for Building Research Data and Software Competencies. INFORMATIK Maryam Movahedifar, Lena Steinmann, Rolf Drechsler
2025	J	`jnl`	LLM-assisted Bug Identification and Correction for Verilog HDL. ACM Trans. Design Autom. Electr. Syst. Khushboo Qayyum, Chandan Kumar Jha, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
2025	C	`conf`	LLM-assisted Performance Estimation of Embedded Software on RISC-V Processors. DDECS Weiyan Zhang, Muhammad Hassan, Rolf Drechsler
2025	J	`jnl`	LLM-based Behaviour Driven Development for Hardware Design. CoRR Rolf Drechsler, Qian Liu
2025	B	`conf`	Large Language Models (LLMs) for Verification, Testing, and Design. ETS Chandan Kumar Jha, Muhammad Hassan, Khushboo Qayyum, Sallar Ahmadi-Pour, Kangwei Xu, Ruidi Qiu, Jason Blocklove, Luca Collini, Andre Nakkab, Ulf Schlichtmann, Grace Li Zhang, Ramesh Karri, Bing Li, Siddharth Garg, Rolf Drechsler
2025	A	`conf`	Late Breaking Results: Towards Efficient Formal Verification of Dot Product Architectures. DATE Lennart Weingarten, Kamalika Datta, Rolf Drechsler
2025	J	`jnl`	Lower bound proof for the size of BDDs representing a shifted addition. Inf. Process. Lett. Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler
2025	J	`jnl`	MESSI: Task Mapping and Scheduling Strategy for FPGA-based Heterogeneous Real-Time Systems. ACM Trans. Design Autom. Electr. Syst. Sallar Ahmadi-Pour, Sangeet Saha, Klaus D. McDonald-Maier, Rolf Drechsler
2025	—	`conf`	Multi-Input MAGIC Synthesis and Verification for In-Memory Computing Design. ISMVL Saeideh Nabipour, Kamalika Datta, Lennart Weingarten, Abhoy Kole, Rolf Drechsler
2025	J	`jnl`	OPTI-Sim: Performing Optical Probing Simulation on Layout Design Files. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
2025	J	`jnl`	Polynomial Formal Verification of Multi-Valued Approximate Circuits Within Constant Cutwidth. IEEE Trans. Circuits Syst. I Regul. Pap. Mohamed A. Nadeem, Chandan Kumar Jha, Rolf Drechsler
2025	A	`conf`	Polynomial Formal Verification of Sequential Circuits Using Weighted-AIGs. DATE Mohamed A. Nadeem, Chandan Kumar Jha, Rolf Drechsler
2025	—	`conf`	Preserving and Improving Verifiability of Circuits Based on Local Transformations. LATS Rolf Drechsler
2025	—	`conf`	Prompt. Verify. Repeat. LLMs in the Hardware Verification Cycle. COINS Muhammad Hassan, Mohamed A. Nadeem, Khushboo Qayyum, Chandan Kumar Jha, Rolf Drechsler
2025	A	`conf`	Revolution or Hype? Seeking the Limits of Large Models in Hardware Design. ICCAD Qiang Xu, Leon Stok, Rolf Drechsler, Xi Wang, Grace Li Zhang, Igor L. Markov
2025	J	`jnl`	Revolution or Hype? Seeking the Limits of Large Models in Hardware Design. CoRR Qiang Xu, Leon Stok, Rolf Drechsler, Xi Wang, Grace Li Zhang, Igor L. Markov
2025	C	`conf`	River: Sneak Path Aware READ-based In-Memory Computing for 1T1M Memristive Crossbars. DDECS Till Schnittka, Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler
2025	—	`conf`	Special Session Paper: Application of Functional Verification Techniques in Hardware Trust. DFT Mohammad Reza Heidari Iman, Rolf Drechsler, Chandan Kumar Jha, Ali Azarpeyvand, Tara Ghasempouri, Sharjeel Imtiaz, Jaan Raik, Samuele Germiniani, Daniele Nicoletti, Graziano Pravadelli, Giorgio Di Natale
2025	—	`conf`	Special Session Paper: Formal Verification Techniques and Reliability Methods for RRAM-based Computing-in-Memory. DFT Chandan Kumar Jha, Sumit Kumar Jha, Ulf Schlichtmann, Rolf Drechsler
2025	C	`conf`	Synthesis for Testability: Polynomial Test Pattern Generation for KFDD Circuits. DSD Martha Schnieber, Rolf Drechsler
2025	C	`conf`	System-Level Design Space Exploration for Matrix Multiplication using Compute-In-Memory Unit. FDL Deepak Ravibabu, Sallar Ahmadi-Pour, Muhammad Hassan, Abhoy Kole, Chandan Kumar Jha, Rolf Drechsler
2025	J	`jnl`	Towards LLM-based Generation of Human-Readable Proofs in Polynomial Formal Verification. CoRR Rolf Drechsler
2025	C	`conf`	Towards an Automated Debugging Approach for Fault Identification in Quantum Circuits. DDECS Anton Maidl, Abhoy Kole, Kamalika Datta, Jannis Stoppe, Rolf Drechsler
2025	Misc	`conf`	True-PolyTronik: Securing Circuits Against Laser Logic State Imaging Attack Using RFET. VLSID Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler
2025	—	`conf`	Unlocking the Benefits of Dynamic Quantum Circuits in Resource Constraint Architecture. ISVLSI Abhoy Kole, Mohammed E. Djeridane, Arighna Deb, Kamalika Datta, Indranil Sengupta, Rolf Drechsler
2025	J	`jnl`	qSAT: Design of an Efficient Quantum Satisfiability Solver for Hardware Equivalence Checking. ACM J. Emerg. Technol. Comput. Syst. Abhoy Kole, Mohammed E. Djeridane, Lennart Weingarten, Kamalika Datta, Rolf Drechsler
2024	Misc	`conf`	A Dynamic Programming Based Graph Traversal Approach for Efficient Implementation of Nearest Neighbor Architecture in 2D. VLSID Sneha Lahiri, Megha Kesh, Rupsa Mandal, Anirban Bhattacharjee, Sovan Bhattacharya, Dola Sinha, Chandan Bandyopadhyay, Laxmidhar Biswal, Robert Wille, Rolf Drechsler
2024	B	`conf`	A Multi-Objective Evolutionary Approach for Test Network Design. ETS Payam Habiby, Fatemeh Shirinzadeh, Sebastian Huhn, Rolf Drechsler
2024	—	`conf`	Aufbau einer überregionalen Data-Science-Community. INFORMATIK Helen Pfuhl, Lena Steinmann, Dirk Nowotka, Rolf Drechsler
2024	—	`conf`	AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design. MLCAD Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li
2024	J	`jnl`	AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design. CoRR Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li
2024	J	`jnl`	BinSym: Binary-Level Symbolic Execution using Formal Descriptions of Instruction Semantics. CoRR Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler
2024	A	`conf`	Complete and Efficient Verification for a RISC-V Processor Using Formal Verification. DATE Lennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler
2024	J	`jnl`	CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design. CoRR Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li
2024	—	`conf`	Design Automation Challenges and Benefits of Dynamic Quantum Circuit in Present NISQ Era and Beyond: (Invited Paper). ISVLSI Abhoy Kole, Kamalika Datta, Rolf Drechsler
2024	J	`jnl`	Determining the Effect of Feedback Quality on User Engagement on Online Idea Crowdsourcing Platforms Using an AI model. Proc. ACM Hum. Comput. Interact. Sana Hassan Imam, Christopher A. Metz, Lars Hornuf, Rolf Drechsler
2024	A	`conf`	Dynamic Realization of Multiple Control Toffoli Gate. DATE Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler
2024	J	`jnl`	Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL. ACM Trans. Embed. Comput. Syst. Mehran Goli, Rolf Drechsler
2024	A*	`conf`	Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent. DAC Kemal Çaglar Coskun, Muhammad Hassan, Lars Hedrich, Rolf Drechsler
2024	J	`jnl`	EnR: extend and reduce methodology to enable formal verification of truncated adders. it Inf. Technol. Chandan Kumar Jha, Khushboo Qayyum, Muhammad Hassan, Rolf Drechsler
2024	J	`jnl`	EvoAl CoRR Bernhard J. Berger, Christina Plump, Rolf Drechsler
2024	—	`conf`	EvoAl - Codeless Domain-Optimisation. GECCO Companion Bernhard Johannes Berger, Christina Plump, Lauren Paul, Rolf Drechsler
2024	Misc	`conf`	Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. VLSID Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana
2024	J	`jnl`	Exploiting the Extended Neighborhood of Hexagonal Qubit Architecture for Mapping Quantum Circuits. ACM J. Emerg. Technol. Comput. Syst. Abhoy Kole, Kamalika Datta, Indranil Sengupta, Rolf Drechsler
2024	—	`conf`	Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification. ACM Great Lakes Symposium on VLSI Khushboo Qayyum, Abhoy Kole, Kamalika Datta, Muhammad Hassan, Rolf Drechsler
2024	—	`conf`	Exploring the Potential of Dynamic Quantum Circuit for Improving Device Scalability. SOCC Abhoy Kole, Kamalika Datta, Rolf Drechsler
2024	B	`conf`	Finding the perfect MRI sequence for your patient - Towards an optimisation workflow for MRI-sequences. CEC Christina Plump, Daniel Christopher Hoinkiss, Jörn Huber, Bernhard J. Berger, Matthias Günther, Christoph Lüth, Rolf Drechsler
2024	A	`conf`	Hidden Cost of Circuit Design with RFETs. DATE Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler
2024	—	`conf`	Improving Self-Fault-Tolerance Capability of Memristor Crossbar Using a Weight-Sharing Approach. ATS Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, F. Lalchhandama, Kamalika Datta, Rolf Drechsler, Indranil Sengupta
2024	C	`conf`	Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences. DDECS Jan Zielasko, Rune Krauss, Marcel Merten, Rolf Drechsler
2024	C	`conf`	In-Memory Mirroring: Cloning Without Reading. VLSI-SoC Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant
2024	J	`jnl`	In-Memory Mirroring: Cloning Without Reading. CoRR Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant
2024	Misc	`conf`	In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures. VLSID Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta, Rolf Drechsler
2024	Misc	`conf`	Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic. VLSID Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler
2024	C	`conf`	Is Simulation the only Alternative for Effective Verification of Dynamic Quantum Circuits? RC Liam Hurwitz, Kamalika Datta, Abhoy Kole, Rolf Drechsler
2024	A	`conf`	LLM-Guided Formal Verification Coupled with Mutation Testing. DATE Muhammad Hassan, Sallar Ahmadi-Pour, Khushboo Qayyum, Chandan Kumar Jha, Rolf Drechsler
2024	—	`conf`	LLMs for Hardware Verification: Frameworks, Techniques, and Future Directions. ATS Khushboo Qayyum, Sallar Ahmadi-Pour, Chandan Kumar Jha, Muhammad Hassan, Rolf Drechsler
2024	A*	`conf`	Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification. DAC Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler
2024	J	`jnl`	Lower the RISC: Designing optical-probing-attack-resistant cores. Microprocess. Microsystems Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler
2024	B	`conf`	MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. ASPDAC Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
2024	B	`conf`	Polynomial Formal Verification of Approximate Adders with Constant Cutwidth. ETS Mohamed A. Nadeem, Chandan Kumar Jha, Rolf Drechsler
2024	J	`jnl`	Polynomial Formal Verification of Arithmetic Circuits. Found. Trends Electron. Des. Autom. Alireza Mahzoon, Rolf Drechsler
2024	—	`conf`	Polynomial Formal Verification of Multi-Valued Logic Circuits within Constant Cutwidth Architectures. ISMVL Mohamed A. Nadeem, Rolf Drechsler
2024	A	`conf`	Polynomial Formal Verification of Sequential Circuits. DATE Caroline Dominik, Rolf Drechsler
2024	—	`conf`	Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study. NorCAS Mohammad Reza Heidari Iman, Sallar Ahmadi-Pour, Rolf Drechsler, Tara Ghasempouri
2024	J	`jnl`	ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars. ACM Trans. Embed. Comput. Syst. Kousik Bhunia, Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler
2024	C	`conf`	SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited Cutwidth. DSD Luca Müller, Rolf Drechsler
2024	B	`conf`	Security Coverage Metrics for Information Flow at the System Level. ASPDAC Ece Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
2024	J	`jnl`	Solving Boolean Problems and Beyond. it Inf. Technol. Rolf Drechsler, Görschwin Fey
2024	—	`conf`	The Future is Hybrid: Next Generation Data Structures for Formal Verification. ATS Rolf Drechsler, Christina Plump, Martha Schnieber
2024	—	`conf`	Towards Formal Verification for MAC-based In-Memory Computing. ATS Fatemeh Shirinzadeh, Kamalika Datta, Saeideh Shirinzadeh, Abhoy Kole, Rolf Drechsler
2024	—	`conf`	Towards Polynomial Formal Verification of Neuromorphic Architectures. ISED Lennart Weingarten, Kamalika Datta, Rolf Drechsler
2024	J	`jnl`	Why less is sometimes more: Using Boolean literals to solve 2048. it Inf. Technol. Bernhard J. Berger, Christina Plump, Rolf Drechsler
2024	J	`jnl`	cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Chandan Kumar Jha, Muhammad Hassan, Rolf Drechsler
2024	J	`jnl`	qSAT: Design of an Efficient Quantum Satisfiability Solver for Hardware Equivalence Checking. CoRR Abhoy Kole, Mohammed E. Djeridane, Lennart Weingarten, Kamalika Datta, Rolf Drechsler
2024	J	`jnl`	veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap. Chandan Kumar Jha, Khushboo Qayyum, Kemal Çaglar Coskun, Simranjeet Singh, Muhammad Hassan, Rainer Leupers, Farhad Merchant, Rolf Drechsler
2023	—	`conf`	Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars. ASP-DAC Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler
2023	—	`conf`	Automated Polynomial Formal Verification: Human-Readable Proof Generation. iSES Rolf Drechsler, Martha Schnieber
2023	—	`conf`	Benchmarking Multiplier Architectures for MAGIC Based In-Memory Computing. NEWCAS Chandan Kumar Jha, Rolf Drechsler
2023	—	`conf`	Classifying Crowdsouring Platform Users' Engagement Behaviour using Machine Learning and XAI. MuC (Workshopband) Sana Hassan Imam, Christopher A. Metz, Lars Hornuf, Rolf Drechsler
2023	—	`conf`	Coverage-Guided Fuzzing for Plan-Based Robotics. ICAART (2) Tim Meywerk, Vladimir Herdt, Rolf Drechsler
2023	A	`conf`	Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors. DATE Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed E. Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, V. Sessi, M. Drescher, S. Kolodinski, M. Wiatr
2023	A	`conf`	Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex Circuits. DATE Rolf Drechsler, Alireza Mahzoon
2023	—	`conf`	EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation. ASP-DAC Rune Krauss, Mehran Goli, Rolf Drechsler
2023	B	`conf`	EVOAL: A Domain-Specific Language-Based Approach to Optimisation. CEC Bernhard J. Berger, Christina Plump, Rolf Drechsler
2023	C	`conf`	Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes. DDECS Rune Krauss, Mehran Goli, Rolf Drechsler
2023	C	`conf`	Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V Processors. DSD Weiyan Zhang, Mehran Goli, Muhammad Hassan, Rolf Drechsler
2023	A	`conf`	Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits. DATE Kemal Çaglar Coskun, Muhammad Hassan, Rolf Drechsler
2023	J	`jnl`	Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. CoRR Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana
2023	C	`conf`	Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures. RC Abhoy Kole, Kamalika Datta, Philipp Niemann, Indranil Sengupta, Rolf Drechsler
2023	A	`conf`	Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network. DATE Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler
2023	A	`conf`	FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing. DATE Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
2023	—	`conf`	Fast and Accurate: Machine Learning Techniques for Performance Estimation of CNNs for GPGPUs. IPDPS Workshops Christopher A. Metz, Mehran Goli, Rolf Drechsler
2023	—	`conf`	Finite State Automata Design using 1T1R ReRAM Crossbar. NEWCAS Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant
2023	J	`jnl`	Finite State Automata Design using 1T1R ReRAM Crossbar. CoRR Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant
2023	C	`conf`	Hybrid PTX Analysis for GPU accelerated CNN inferencing aiding Computer Architecture Design. FDL Christopher A. Metz, Christina Plump, Bernhard J. Berger, Rolf Drechsler
2023	C	`conf`	Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification. FDL Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
2023	J	`jnl`	Impact of sneak paths on in-memory logic design in memristive crossbars. it Inf. Technol. Kamalika Datta, Arighna Deb, Abhoy Kole, Rolf Drechsler
2023	C	`conf`	Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture. RC Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler
2023	B	`conf`	Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods. ETS Marcel Merten, Sebastian Huhn, Rolf Drechsler
2023	—	`conf`	LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing. ISVLSI Sajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler
2023	—	`conf`	Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core. COINS Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler
2023	J	`jnl`	MARADIV: Library of MAGIC-Based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors. IEEE Trans. Circuits Syst. II Express Briefs Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler
2023	J	`jnl`	MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. CoRR Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
2023	—	`conf`	Memristors: Device Modeling, Design and Verification. iSES Kamalika Datta, Rolf Drechsler
2023	C	`conf`	Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models. FDL Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler
2023	C	`conf`	Next-Generation Automatic Human-Readable Proofs Enabling Polynomial Formal Verification. MEMOCODE Rolf Drechsler, Martha Schnieber
2023	—	`conf`	PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor. NANOARCH Lennart Weingarten, Kamalika Datta, Rolf Drechsler
2023	C	`conf`	Polynomial Formal Verification exploiting Constant Cutwidth. RSP Mohamed A. Nadeem, Jan Kleinekathöfer, Rolf Drechsler
2023	—	`conf`	Polynomial Formal Verification of Complex Circuits Using a Hybrid Proof Engine. Applicable Formal Methods for Safe Industrial Products Alireza Mahzoon, Rolf Drechsler
2023	A	`conf`	Polynomial Formal Verification of Floating Point Adders. DATE Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler
2023	C	`conf`	Polynomial Formal Verification of KFDD Circuits. MEMOCODE Martha Schnieber, Rolf Drechsler
2023	—	`conf`	Polynomial Formal Verification of a Processor: A RISC-V Case Study. ISQED Lennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler
2023	A	`conf`	Processor Verification using Symbolic Execution: A RISC-V Case-Study. DATE Niklas Bruns, Vladimir Herdt, Rolf Drechsler
2023	C	`conf`	Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques. DDECS Marcel Merten, Muhammad Hassan, Rolf Drechsler
2023	—	`conf`	RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan Networks. DFT Payam Habiby, Sebastian Huhn, Rolf Drechsler
2023	—	`conf`	Repetitive Processes and Their Surrogate-Model Congruent Encoding for Evolutionary Algorithms - A Theoretic Proposal. GECCO Companion Christina Plump, Bernhard J. Berger, Rolf Drechsler
2023	—	`conf`	Scalable Neuroevolution of Ensemble Learners. GECCO Companion Marcel Merten, Rune Krauss, Rolf Drechsler
2023	J	`jnl`	Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. CoRR Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
2023	J	`jnl`	Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. IEEE Embed. Syst. Lett. Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant
2023	J	`jnl`	Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT. IEEE Internet Things J. Sören Tempel, Vladimir Herdt, Rolf Drechsler
2023	B	`conf`	Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips. ETS Payam Habiby, Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich, Sebastian Huhn, Rolf Drechsler
2023	—	`conf`	Towards Polynomial Formal Verification of AI-Generated Arithmetic Circuits. ISDCS Rolf Drechsler, Alireza Mahzoon
2023	—	`conf`	Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study. ASP-DAC Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
2023	—	`conf`	VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking. ISQED Ece Nur Demirhan Coskun, Muhammad Hassan, Mehran Goli, Rolf Drechsler
2023	—	`conf`	Verification of In-Memory Logic Design using ReRAM Crossbars. NEWCAS Kamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler
2023	C	`conf`	Virtual Prototype Driven Application Specific Hardware Optimization. FDL Jan Zielasko, Rolf Drechsler
2023	J	`jnl`	Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap. CoRR Sallar Ahmadi-Pour, Pascal Pieper, Rolf Drechsler
2023	—	`conf`	Workshop: "Aktuelle Entwicklungen und Perspektiven (an Hochschulen) im Bereich Data Science". GI-Jahrestagung Lena Steinmann, Dirk Nowotka, Lea Oberländer, Helen Pfuhl, Heiner Stuckenschmidt, Rolf Drechsler
2022	C	`conf`	3D Visualization of Symbolic Execution Traces. FDL Jan Zielasko, Sören Tempel, Vladimir Herdt, Rolf Drechsler
2022	Misc	`conf`	A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection. VTS Marcel Merten, Sebastian Huhn, Rolf Drechsler
2022	C	`conf`	ANN-based Performance Estimation of Embedded Software for RISC-V Processors. RSP Weiyan Zhang, Mehran Goli, Alireza Mahzoon, Rolf Drechsler
2022	—	`conf`	Adapting mutation and recombination operators to range-aware relations in real-world application data. GECCO Companion Christina Plump, Bernhard J. Berger, Rolf Drechsler
2022	—	`conf`	Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype. ACM Great Lakes Symposium on VLSI Pascal Pieper, Vladimir Herdt, Rolf Drechsler
2022	J	`jnl`	Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges. Sci. China Inf. Sci. Vladimir Herdt, Rolf Drechsler
2022	—	`conf`	Automated Detection of Spatial Memory Safety Violations for Constrained Devices. ASP-DAC Sören Tempel, Vladimir Herdt, Rolf Drechsler
2022	J	`jnl`	CoMIC: Complementary Memristor based in-memory computing in 3D architecture. J. Syst. Archit. F. Lalchhandama, Kamalika Datta, Sandip Chakraborty, Rolf Drechsler, Indranil Sengupta
2022	A	`conf`	Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging. DATE Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler
2022	—	`ch.`	Das Bremen Ambient Assisted Living Lab und darüber hinaus - Intelligente Umgebungen, smarte Services und Künstliche Intelligenz in der Medizin für den Menschen. Künstliche Intelligenz im Gesundheitswesen Serge Autexier, Christoph Lüth, Rolf Drechsler
2022	B	`conf`	Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization. FMCAD Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler
2022	C	`conf`	Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression. DDECS Weiyan Zhang, Mehran Goli, Rolf Drechsler
2022	—	`conf`	Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing. ACM Great Lakes Symposium on VLSI Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
2022	C	`conf`	Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters. DDECS Kemal Çaglar Coskun, Muhammad Hassan, Rolf Drechsler
2022	J	`jnl`	FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications. J. Electron. Test. Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta, Sandip Chakraborty, Rolf Drechsler, Indranil Sengupta
2022	—	`conf`	Fast and Exact is Doable: Polynomial Algorithms in Test and Verification. LATS Rolf Drechsler
2022	J	`jnl`	Feed-Forward learning algorithm for resistive memories. J. Syst. Archit. Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta, Sandip Chakraborty, Rolf Drechsler, Indranil Sengupta
2022	A*	`conf`	Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. DAC Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler
2022	C	`conf`	Generation of Verified Programs for In-Memory Computing. DSD Saman Fröhlich, Rolf Drechsler
2022	J	`jnl`	Introduction to the Special Issue on Design Automation for Quantum Computing. ACM J. Emerg. Technol. Comput. Syst. Robert Wille, Rolf Drechsler
2022	A	`conf`	LiM-HDL: HDL-Based Synthesis for In-Memory Computing. DATE Saman Fröhlich, Rolf Drechsler
2022	J	`jnl`	Lower Bound Proof for the Size of BDDs representing a Shifted Addition. CoRR Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler
2022	C	`conf`	ML-based Power Estimation of Convolutional Neural Networks on GPGPUs. DDECS Christopher A. Metz, Mehran Goli, Rolf Drechsler
2022	—	`conf`	Mapping Quantum Circuits to 2-Dimensional Quantum Architectures. GI-Jahrestagung Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler
2022	—	`conf`	Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal Qubit Architecture. ISMVL Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler
2022	A	`conf`	Next Generation Design For Testability, Debug and Reliability Using Formal Techniques. ITC Sebastian Huhn, Rolf Drechsler
2022	J	`jnl`	Parallel Computing of Graph-based Functions in ReRAM. ACM J. Emerg. Technol. Comput. Syst. Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
2022	C	`conf`	Polynomial Formal Verification of Approximate Adders. DSD Martha Schnieber, Saman Fröhlich, Rolf Drechsler
2022	—	`conf`	Polynomial Formal Verification of Approximate Functions. ISVLSI Martha Schnieber, Saman Fröhlich, Rolf Drechsler
2022	—	`conf`	Polynomial Formal Verification of Complex Multipliers. MBMV Alireza Mahzoon, Rolf Drechsler
2022	A	`conf`	Polynomial Formal Verification: Ensuring Correctness under Resource Constraints. ICCAD Rolf Drechsler, Alireza Mahzoon
2022	—	`conf`	Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic. ISMVL Philipp Niemann, Rolf Drechsler
2022	C	`conf`	Preserving Design Hierarchy Information for Polynomial Formal Verification. VLSI-SoC Rolf Drechsler, Alireza Mahzoon
2022	B	`conf`	Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods. ETS Marcel Merten, Sebastian Huhn, Rolf Drechsler
2022	J	`jnl`	RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alireza Mahzoon, Daniel Große, Rolf Drechsler
2022	C	`conf`	SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library. DSD Abhoy Kole, Kamalika Datta, Indranil Sengupta, Rolf Drechsler
2022	B	`conf`	SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. ATVA Sören Tempel, Vladimir Herdt, Rolf Drechsler
2022	—	`conf`	Self-Explanation in Systems of Systems. RE Workshops Görschwin Fey, Martin Fränzle, Rolf Drechsler
2022	—	`conf`	Simulation-Based Debugging of Formal Environment Models. MED Tim Meywerk, Arthur Niedzwiecki, Vladimir Herdt, Rolf Drechsler
2022	—	`conf`	Simulation-based Verification of SystemC-based VPs at the ESL. MBMV Mehran Goli, Rolf Drechsler
2022	J	`jnl`	Simulation-based Verification of SystemC-based VPs at the ESL. CoRR Mehran Goli, Rolf Drechsler
2022	J	`jnl`	SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware. J. Syst. Archit. Sören Tempel, Vladimir Herdt, Rolf Drechsler
2022	C	`conf`	Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study. DSD Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler, Klaus D. McDonald-Maier
2022	J	`jnl`	Template-based mapping of reversible circuits to IBM quantum computers. Microprocess. Microsystems Philipp Niemann, Alexandre A. A. de Almeida, Gerhard W. Dueck, Rolf Drechsler
2022	J	`jnl`	The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research. J. Syst. Archit. Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
2022	A	`conf`	The Scale4Edge RISC-V Ecosystem. DATE Wolfgang Ecker, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jörg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz
2022	J	`jnl`	Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mehran Goli, Rolf Drechsler
2022	—	`conf`	Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques. ASP-DAC Sajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler
2022	—	`conf`	Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency Scaling. MLCAD Christopher A. Metz, Mehran Goli, Rolf Drechsler
2022	C	`conf`	Towards Polynomial Formal Verification of Complex Arithmetic Circuits. DDECS Rolf Drechsler, Alireza Mahzoon, Mehran Goli
2022	J	`jnl`	Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing. IEEE Embed. Syst. Lett. Sören Tempel, Vladimir Herdt, Rolf Drechsler
2022	C	`conf`	Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification. FDL Niklas Bruns, Vladimir Herdt, Rolf Drechsler
2022	C	`conf`	Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications. VLSI-SoC Kamalika Datta, Saman Fröhlich, Saeideh Shirinzadeh, Dev Narayan Yadav, Indranil Sengupta, Rolf Drechsler
2022	C	`conf`	Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles. DSD Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta, Rolf Drechsler
2022	J	`jnl`	Unlocking approximation for in-memory computing with Cartesian genetic programming and computer algebra for arithmetic circuits. it Inf. Technol. Saman Fröhlich, Rolf Drechsler
2022	B	`conf`	Using density of training data to improve evolutionary algorithms with approximative fitness functions. CEC Christina Plump, Bernhard J. Berger, Rolf Drechsler
2022	A*	`conf`	Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. DAC Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
2022	C	`conf`	Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device. FDL Alexander Fratzer, Vladimir Herdt, Christoph Lüth, Rolf Drechsler
2022	C	`conf`	Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions. DDECS Milan Funck, Vladimir Herdt, Rolf Drechsler
2021	—	`conf`	A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks. DFT Marcel Merten, Sebastian Huhn, Rolf Drechsler
2021	J	`jnl`	ALF - A Fitness-Based Artificial Life Form for Evolving Large-Scale Neural Networks. CoRR Rune Krauss, Marcel Merten, Mirco Bockholt, Rolf Drechsler
2021	—	`conf`	ALF: a fitness-based artificial life form for evolving large-scale neural networks. GECCO Companion Rune Krauss, Marcel Merten, Mirco Bockholt, Rolf Drechsler
2021	—	`conf`	ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs. ASP-DAC Mehran Goli, Rolf Drechsler
2021	J	`jnl`	Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform. J. Syst. Archit. Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
2021	A	`conf`	An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes. DATE Sören Tempel, Vladimir Herdt, Rolf Drechsler
2021	J	`jnl`	An ant colony based mapping of quantum circuits to nearest neighbor architectures. Integr. Anirban Bhattacharjee, Chandan Bandyopadhyay, Angshu Mukherjee, Robert Wille, Rolf Drechsler, Hafizur Rahaman
2021	J	`jnl`	An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture. Integr. Anirban Bhattacharjee, Chandan Bandyopadhyay, Philipp Niemann, Bappaditya Mondal, Rolf Drechsler, Hafizur Rahaman
2021	C	`conf`	Automated Debugging-Aware Visualization Technique for SystemC HLS Designs. DSD Mehran Goli, Alireza Mahzoon, Rolf Drechsler
2021	C	`conf`	Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation. DSD Philipp Niemann, Luca Müller, Rolf Drechsler
2021	A	`conf`	Combining SWAPs and Remote Toffoli Gates in the Mapping to IBM QX Architectures. DATE Philipp Niemann, Chandan Bandyopadhyay, Rolf Drechsler
2021	—	`conf`	Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion. MBMV Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
2021	—	`conf`	Depth Optimized Synthesis of Symmetric Boolean Functions. ISVLSI Martha Schnieber, Saman Fröhlich, Rolf Drechsler
2021	B	`conf`	Domain-driven Correlation-aware Recombination and Mutation Operators for Complex Real-world Applications. CEC Christina Plump, Bernhard J. Berger, Rolf Drechsler
2021	A	`conf`	Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs. ICCAD Mehran Goli, Rolf Drechsler
2021	Misc	`conf`	Early power estimation of CUDA-based CNNs on GPGPUs: work-in-progress. CODES+ISSS Christopher A. Metz, Mehran Goli, Rolf Drechsler
2021	C	`conf`	Finding Optimal Implementations of Non-native CNOT Gates Using SAT. RC Philipp Niemann, Luca Müller, Rolf Drechsler
2021	B	`conf`	Improving Evolutionary Algorithms by Enhancing an Approximative Fitness Function through Prediction Intervals. CEC Christina Plump, Bernhard J. Berger, Rolf Drechsler
2021	C	`conf`	In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. FDL Sören Tempel, Vladimir Herdt, Rolf Drechsler
2021	A*	`conf`	Late Breaking Results: Polynomial Formal Verification of Fast Adders. DAC Alireza Mahzoon, Rolf Drechsler
2021	C	`conf`	Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level. VLSI-SoC Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler
2021	—	`conf`	Minimally Invasive HW/SW Co-debug Live Visualization on Architecture Level. ACM Great Lakes Symposium on VLSI Pascal Pieper, Ralf Wimmer, Gerhard Angst, Rolf Drechsler
2021	—	`conf`	Mutation-based Compliance Testing for RISC-V. ASP-DAC Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler
2021	A	`conf`	Nano Security: From Nano-Electronics to Secure Systems. DATE Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer
2021	—	`ch.`	Non-Clausal SAT and ATPG. Handbook of Satisfiability Rolf Drechsler, Tommi A. Junttila, Ilkka Niemelä
2021	—	`conf`	One-pass Synthesis for Field-coupled Nanocomputing Technologies. ASP-DAC Marcel Walter, Winston Haaswijk, Robert Wille, Frank Sill Torres, Rolf Drechsler
2021	—	`conf`	Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability. DTIS Payam Habiby, Sebastian Huhn, Rolf Drechsler
2021	C	`conf`	Performance Aspects of Correctness-oriented Synthesis Flows. MODELSWARD Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
2021	J	`jnl`	Pick the Right Edge Device: Towards Power and Performance Estimation of CUDA-based CNNs on GPGPUs. CoRR Christopher A. Metz, Mehran Goli, Rolf Drechsler
2021	C	`conf`	PolyAdd: Polynomial Formal Verification of Adder Circuits. DDECS Rolf Drechsler
2021	J	`jnl`	Polynomial Circuit Verification using BDDs. CoRR Rolf Drechsler
2021	—	`conf`	Polynomial Formal Verification of Prefix Adders. ATS Alireza Mahzoon, Rolf Drechsler
2021	C	`conf`	Polynomial word-level verification of arithmetic circuits. MEMOCODE Mohammed Barhoush, Alireza Mahzoon, Rolf Drechsler
2021	C	`conf`	RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems. FDL Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
2021	—	`conf`	Synthesis of Asymptotically Optimal Adders for Multiple-Valued Logic. ISMVL Philipp Niemann, Rolf Drechsler
2021	A	`conf`	System Level Verification of Phase-Locked Loop using Metamorphic Relations. DATE Muhammad Hassan, Daniel Große, Rolf Drechsler
2021	—	`conf`	System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations. ASP-DAC Muhammad Hassan, Daniel Große, Rolf Drechsler
2021	J	`jnl`	Toward RISC-V CSR Compliance Testing. IEEE Embed. Syst. Lett. Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
2021	A*	`conf`	Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing. DAC Sören Tempel, Vladimir Herdt, Rolf Drechsler
2021	C	`conf`	VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes. FDL Mehran Goli, Rolf Drechsler
2021	A	`conf`	Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization. DATE Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, Rolf Drechsler
2021	A	`conf`	Vertical IP Protection of the Next-Generation Devices: Quo Vadis? DATE Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar
2021	C	`conf`	XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding. ISCAS Lucas Klemmer, Saman Fröhlich, Rolf Drechsler, Daniel Große
2020	C	`conf`	ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique. ICCD Mehran Goli, Alireza Mahzoon, Rolf Drechsler
2020	—	`conf`	ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks. ISMVL Saman Fröhlich, Lucas Klemmer, Daniel Große, Rolf Drechsler
2020	C	`conf`	Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. ICCD Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
2020	J	`jnl`	Advanced exact synthesis of Clifford+T circuits. Quantum Inf. Process. Philipp Niemann, Robert Wille, Rolf Drechsler
2020	—	`conf`	Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and Visualization. ISVLSI Mehran Goli, Rolf Drechsler
2020	J	`jnl`	Automated Nonintrusive Analysis of Electronic System Level Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mehran Goli, Jannis Stoppe, Rolf Drechsler
2020	—	`conf`	Bail on Balancing: An Alternative Approach to the Physical Design of Field-Coupled Nanocomputing Circuits. ISVLSI Marcel Walter, Robert Wille, Frank Sill Torres, Rolf Drechsler
2020	A*	`conf`	Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side DAC Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	B	`conf`	Clustering-Guided SMT($\mathcal {L\!R\!A}$) Learning. IFM Tim Meywerk, Marcel Walter, Daniel Große, Rolf Drechsler
2020	C	`conf`	Combining Machine Learning and Formal Techniques for Small Data Applications - A Framework to Explore New Structural Materials. DSD Rolf Drechsler, Sebastian Huhn, Christina Plump
2020	—	`conf`	Design Automation for Field-Coupled Nanotechnologies. ISVLSI Marcel Walter, Rolf Drechsler
2020	C	`conf`	Design Space Exploration in the Mapping of Reversible Circuits to IBM Quantum Computers. DSD Philipp Niemann, Alexandre A. A. de Almeida, Gerhard W. Dueck, Rolf Drechsler
2020	A*	`conf`	Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes. DAC Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	—	`conf`	Early Verification of ISA Extension Specifications using Deep Reinforcement Learning. ACM Great Lakes Symposium on VLSI Niklas Bruns, Daniel Große, Rolf Drechsler
2020	C	`conf`	Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study. FDL Vladimir Herdt, Daniel Große, Eyck Jentzsch, Rolf Drechsler
2020	—	`conf`	Efficient Implementation of Nearest Neighbor Quantum Circuits Using Clustering with Genetic Algorithm. ISMVL Anirban Bhattacharjee, Chandan Bandyopadhyay, Angshu Mukherjee, Robert Wille, Rolf Drechsler, Hafizur Rahaman
2020	—	`conf`	Efficient Techniques to Strongly Enhance the Virtual Prototype Based Design Flow. ISVLSI Vladimir Herdt, Rolf Drechsler
2020	—	`conf`	Efficient machine learning through evolving combined deep neural networks. GECCO Companion Rune Krauss, Marcel Merten, Mirco Bockholt, Saman Fröhlich, Rolf Drechsler
2020	A	`conf`	Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes DATE Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	A	`conf`	Impacts of Creating Smart Everyday Objects on Young Female Students' Programming Skills and Attitudes. SIGCSE Mazyar Seraj, Eva-Sophie Katterfeldt, Serge Autexier, Rolf Drechsler
2020	C	`conf`	Integer Overflow Detection in Hardware Designs at the Specification Level. MODELSWARD Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
2020	C	`conf`	Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars. ISCAS Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
2020	J	`jnl`	Near Zero-Energy Computation Using Quantum-Dot Cellular Automata. ACM J. Emerg. Technol. Comput. Syst. Frank Sill Torres, Philipp Niemann, Robert Wille, Rolf Drechsler
2020	J	`jnl`	On the Difficulty of Inserting Trojans in Reversible Computing Architectures. IEEE Trans. Emerg. Top. Comput. Xiaotong Cui, Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Kaijie Wu, Rolf Drechsler, Ramesh Karri
2020	J	`jnl`	On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata. Microprocess. Microsystems Frank Sill Torres, Pedro Arthur Silva, Geraldo Fontes, Marcel Walter, José Augusto Miranda Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Robert Wille, Philipp Niemann, Daniel Große, Rolf Drechsler
2020	—	`conf`	One-pass Synthesis for Digital Microfluidic Biochips: A Survey. ISDCS Oliver Keszöcze, Robert Wille, Rolf Drechsler
2020	J	`jnl`	Overcoming the Tradeoff Between Accuracy and Compactness in Decision Diagrams for Quantum Computation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Philipp Niemann, Alwin Zulehner, Rolf Drechsler, Robert Wille
2020	J	`jnl`	PREASC: Automatic Portion Resilience Evaluation for Approximating SystemC-based Designs Using Regression Analysis Techniques. ACM Trans. Design Autom. Electr. Syst. Mehran Goli, Rolf Drechsler
2020	J	`jnl`	PolyAdd: Polynomial Formal Verification of Adder Circuits. CoRR Rolf Drechsler
2020	—	`conf`	Post Synthesis-Optimization of Reversible Circuit using Template Matching. VDAT Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
2020	—	`conf`	Power-aware Test Scheduling for IEEE 1687 Networks with Multiple Power Domains. DFT Payam Habiby, Sebastian Huhn, Rolf Drechsler
2020	J	`jnl`	RISC-V based virtual prototype: An extensible and configurable platform for the system-level. J. Syst. Archit. Vladimir Herdt, Daniel Große, Pascal Pieper, Rolf Drechsler
2020	B	`conf`	RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms. ATVA Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	—	`conf`	Safety First: About the Detection of Arithmetic Overflows in Hardware Design Specifications. MODELSWARD (Revised Selected Papers) Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
2020	C	`conf`	ToPoliNano and fiction: Design Tools for Field-coupled Nanocomputing. DSD Umberto Garlando, Marcel Walter, Robert Wille, Fabrizio Riente, Frank Sill Torres, Rolf Drechsler
2020	—	`conf`	Towards Automatic Hardware Synthesis from Formal Specification to Implementation. ASP-DAC Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
2020	A	`conf`	Towards Formal Verification of Optimized and Industrial Multipliers. DATE Alireza Mahzoon, Daniel Große, Christoph Scholl, Rolf Drechsler
2020	C	`conf`	Towards Generation of a Programmable Power Management Unit at the Electronic System Level. DDECS David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
2020	A	`conf`	Towards Specification and Testing of RISC-V ISA Compliance DATE Vladimir Herdt, Daniel Große, Rolf Drechsler
2020	A	`conf`	Verification Runtime Analysis: Get the Most Out of Partial Verification. DATE Martin Ring, Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
2020	A*	`conf`	Verification for Field-coupled Nanocomputing Circuits. DAC Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
2020	—	`conf`	Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes. ACM Great Lakes Symposium on VLSI Vladimir Herdt, Daniel Große, Jonas Wloka, Tim Güneysu, Rolf Drechsler
2020	—	`conf`	Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling. ISoLA (3) Tim Meywerk, Marcel Walter, Vladimir Herdt, Jan Kleinekathöfer, Daniel Große, Rolf Drechsler
2019	—	`conf`	(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs. ARC Kenneth Schmitz, Buse Ustaoglu, Daniel Große, Rolf Drechsler
2019	—	`conf`	A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems. ITC-Asia Sebastian Huhn, Daniel Tille, Rolf Drechsler
2019	A	`conf`	Accuracy and Compactness in Decision Diagrams for Quantum Computation. DATE Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille
2019	—	`ch.`	Approximate Hardware Generation Using Formal Techniques. Approximate Circuits Saman Fröhlich, Daniel Große, Rolf Drechsler
2019	—	`conf`	Automated Analysis of Virtual Prototypes at Electronic System Level. ACM Great Lakes Symposium on VLSI Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
2019	A	`conf`	Better Late Than Never : Verification of Embedded Systems After Deployment. DATE Martin Ring, Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
2019	—	`conf`	Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements. LATS Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
2019	C	`conf`	Code is Ethics - Formal Techniques for a Better World. DSD Rolf Drechsler, Christoph Lüth
2019	—	`conf`	ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing. NANOARCH Steffen Frerix, Saeideh Shirinzadeh, Saman Fröhlich, Rolf Drechsler
2019	J	`jnl`	Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction. Int. J. Softw. Tools Technol. Transf. Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2019	A	`conf`	Data Flow Testing for SystemC-AMS Timed Data Flow Models. DATE Muhammad Hassan, Daniel Große, Hoang M. Le, Rolf Drechsler
2019	A	`conf`	Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing. DATE Hoang M. Le, Daniel Große, Niklas Bruns, Rolf Drechsler
2019	J	`jnl`	Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits. IEEE Trans. Very Large Scale Integr. Syst. Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler
2019	A*	`conf`	Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study. DAC Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
2019	J	`jnl`	Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019	—	`conf`	Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems. ATS Rolf Drechsler, Daniel Große
2019	J	`jnl`	Evaluation of (power) side-channels in cryptographic implementations. it Inf. Technol. Florian Bache, Christina Plump, Jonas Wloka, Tim Güneysu, Rolf Drechsler
2019	C	`conf`	Functional Coverage-Driven Characterization of RF Amplifiers. FDL Muhammad Hassan, Daniel Große, Thilo Vörtler, Karsten Einwich, Rolf Drechsler
2019	C	`conf`	HotAging - Impact of Power Dissipation on Hardware Degradation. ISCAS Frank Sill Torres, Alberto García Ortiz, Rolf Drechsler
2019	B	`conf`	Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns. ETS Sebastian Huhn, Daniel Tille, Rolf Drechsler
2019	—	`conf`	Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies. ISVLSI Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, Rolf Drechsler
2019	—	`conf`	Impact of NBTI on Increasing the Susceptibility of FinFET to Radiation. IRPS Frank Sill Torres, Hussam Amrouch, Jörg Henkel, Rolf Drechsler
2019	Misc	`conf`	Improved Look-Ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits. VLSID Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
2019	—	`conf`	Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits. ISVLSI Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
2019	—	`conf`	Look what I can do: acquisition of programming skills in the context of living labs. ICSE (SEET) Mazyar Seraj, Cornelia S. Große, Serge Autexier, Rolf Drechsler
2019	B	`conf`	Machine Learning-based Prediction of Test Power. ETS Harshad Dhotre, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
2019	—	`conf`	Maximizing power state cross coverage in firmware-based power management. ASP-DAC Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2019	—	`conf`	One Additional Qubit is Enough: Encoded Embeddings for Boolean Components in Quantum Circuits. ISMVL Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille
2019	J	`jnl`	One Additional Qubit is Enough: Encoded Embeddings for Boolean Components in Quantum Circuits. CoRR Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille
2019	A	`conf`	One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing. DATE Saman Fröhlich, Daniel Große, Rolf Drechsler
2019	J	`jnl`	Placement and Routing for Tile-based Field-coupled Nanocomputing Circuits Is ACM J. Emerg. Technol. Comput. Syst. Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
2019	—	`conf`	Property-Driven Timestamps Encoding for Timeprints-Based Tracing and Monitoring. FORMATS Rehab Massoud, Hoang M. Le, Rolf Drechsler
2019	A*	`conf`	RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. DAC Alireza Mahzoon, Daniel Große, Rolf Drechsler
2019	J	`jnl`	Reversible Circuits: IC/IP Piracy Attacks and Countermeasures. IEEE Trans. Very Large Scale Integr. Syst. Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler, Ramesh Karri
2019	C	`conf`	SAT-Hard: A Learning-Based Hardware SAT-Solver. DSD Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Große, Rolf Drechsler
2019	C	`conf`	Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes. DSD Mehran Goli, Rolf Drechsler
2019	—	`conf`	Scalable design for field-coupled nanocomputing circuits. ASP-DAC Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
2019	—	`conf`	Scratch and Google Blockly: How Girls' Programming Skills and Attitudes are Influenced. Koli Calling Mazyar Seraj, Eva-Sophie Katterfeldt, Kerstin Bub, Serge Autexier, Rolf Drechsler
2019	J	`jnl`	Security validation of VP-based SoCs using dynamic information flow tracking. it Inf. Technol. Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
2019	—	`conf`	Self-Explaining Digital Systems - Some Technical Steps. MBMV Görschwin Fey, Rolf Drechsler
2019	Misc	`conf`	Smart Homes Programming: Development and Evaluation of an Educational Programming Application for Young Learners. IDC Mazyar Seraj, Cornelia S. Große, Serge Autexier, Rolf Drechsler
2019	C	`conf`	Systematic RISC-V based Firmware Design FDL Vladimir Herdt, Daniel Große, Rolf Drechsler, Christoph Gerum, Alexander Louis-Ferdinand Jung, Joscha Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz
2019	—	`conf`	T-depth Optimization for Fault-Tolerant Quantum Circuits. ISMVL Philipp Niemann, Anshu Gupta, Rolf Drechsler
2019	A*	`conf`	Temporal Tracing of On-Chip Signals using Timeprints. DAC Rehab Massoud, Hoang M. Le, Peter Chini, Prakash Saivasan, Roland Meyer, Rolf Drechsler
2019	C	`conf`	Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents. DSD Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Große, Rolf Drechsler
2019	A	`conf`	Verifying Instruction Set Simulators using Coverage-guided Fuzzing DATE Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
2019	J	`jnl`	Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2019	J	`jnl`	fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits. CoRR Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
2018	—	`conf`	A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits. ISVLSI Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
2018	—	`book`	Advanced Logic Synthesis André Inácio Reis, Rolf Drechsler
2018	J	`jnl`	An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Frank Sill Torres, Robert Wille, Philipp Niemann, Rolf Drechsler
2018	A	`conf`	An exact method for design exploration of quantum-dot cellular automata. DATE Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
2018	C	`conf`	Analyzing Frame Conditions in UML/OCL Models - Consistency Equivalence and Independence. MODELSWARD Philipp Niemann, Nils Przigoda, Robert Wille, Rolf Drechsler
2018	A	`conf`	Approximate hardware generation using symbolic computer algebra employing grobner basis. DATE Saman Fröhlich, Daniel Große, Rolf Drechsler
2018	—	`conf`	Approximation-aware testing for approximate circuits. ASP-DAC Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler
2018	—	`book`	Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers Nils Przigoda, Robert Wille, Judith Przigoda, Rolf Drechsler
2018	C	`conf`	Automatic Design of Microfluidic Devices. FDL Robert Wille, Bing Li, Rolf Drechsler, Ulf Schlichtmann
2018	J	`jnl`	Behaviour Driven Development for Hardware Design. IPSJ Trans. Syst. LSI Des. Methodol. Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler
2018	J	`jnl`	Breaking Landauer's Limit\\Using Quantum-dot Cellular Automata. CoRR Frank Sill Torres, Philipp Niemann, Robert Wille, Rolf Drechsler
2018	—	`conf`	Building Fast Multi Agent Systems Using Hardware Design Languages for High-Throughput Systems. LDIC Jannis Stoppe, Christina Plump, Sebastian Huhn, Rolf Drechsler
2018	—	`conf`	Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers. ISVLSI Alireza Mahzoon, Daniel Große, Rolf Drechsler
2018	C	`conf`	Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing. DDECS Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen
2018	—	`ch.`	Emerging Circuit Technologies: An Overview on the Next Generation of Circuits. Advanced Logic Synthesis Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler, Priyank Kalla
2018	C	`conf`	Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata. DSD Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Große, Rolf Drechsler
2018	Misc	`conf`	Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips. VLSID Oliver Keszöcze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
2018	C	`conf`	Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata. DSD Frank Sill Torres, Pedro Arthur Silva, Geraldo Fontes, José Augusto Miranda Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Rolf Drechsler
2018	C	`conf`	Extensible and Configurable RISC-V Based Virtual Prototype. FDL Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
2018	J	`jnl`	Frame conditions in the automatic validation and verification of UML/OCL models: A symbolic formulation of Comput. Lang. Syst. Struct. Nils Przigoda, Philipp Niemann, Jonas Gomes Filho, Robert Wille, Rolf Drechsler
2018	—	`conf`	Generation and Validation of Frame Conditions in Formal Models. MODELSWARD (Revised Selected Papers) Philipp Niemann, Nils Przigoda, Robert Wille, Rolf Drechsler
2018	A	`conf`	IC/IP piracy assessment of reversible logic. ICCAD Samah Mohamed Saeed, Xiaotong Cui, Alwin Zulehner, Robert Wille, Rolf Drechsler, Kaijie Wu, Ramesh Karri
2018	A	`conf`	Improved synthesis of Clifford+T quantum functionality. DATE Philipp Niemann, Robert Wille, Rolf Drechsler
2018	—	`conf`	Keynotes: Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation. IVSW Rolf Drechsler
2018	—	`conf`	Logic Design Using Memristors: An Emerging Technology. ISMVL Saeideh Shirinzadeh, Kamalika Datta, Rolf Drechsler
2018	—	`conf`	Logic Synthesis for In-memory Computing Using Resistive Memories. ISVLSI Saeideh Shirinzadeh, Rolf Drechsler
2018	J	`jnl`	Logic Synthesis for RRAM-Based In-Memory Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
2018	C	`conf`	Multi-objective Synthesis of Quantum Circuits Using Genetic Programming. RC Moein Sarvaghad-Moghaddam, Philipp Niemann, Rolf Drechsler
2018	C	`conf`	Natural Language Based Power Domain Partitioning. DDECS David Lemma, Daniel Große, Rolf Drechsler
2018	J	`jnl`	On the complexity of design tasks for Digital Microfluidic Biochips. Microelectron. J. Oliver Keszöcze, Philipp Niemann, Arved Friedemann, Rolf Drechsler
2018	A	`conf`	PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers. ICCAD Alireza Mahzoon, Daniel Große, Rolf Drechsler
2018	—	`conf`	Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters NORCAS David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
2018	C	`conf`	Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling. IOLTS Robert Schmidt, Rehab Massoud, Jaan Raik, Alberto García Ortiz, Rolf Drechsler
2018	C	`conf`	Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques. RSP Mehran Goli, Jannis Stoppe, Rolf Drechsler
2018	A	`conf`	Resilience evaluation via symbolic fault injection on intermediate code. DATE Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
2018	—	`conf`	SAT-Lancer: A Hardware SAT-Solver for Self-Verification. ACM Great Lakes Symposium on VLSI Buse Ustaoglu, Sebastian Huhn, Daniel Große, Rolf Drechsler
2018	—	`conf`	Synthesis of Reversible Circuits Using Conventional Hardware Description Languages. ISMVL Zaid Al-Wardi, Robert Wille, Rolf Drechsler
2018	J	`jnl`	Synthesis of circuits based on all-optical Mach-Zehnder Interferometers using Binary Decision Diagrams. Microelectron. J. Chandan Bandyopadhyay, Rakesh Das, Robert Wille, Rolf Drechsler, Hafizur Rahaman
2018	A	`conf`	Testbench qualification for SystemC-AMS timed data flow models. DATE Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler
2018	J	`jnl`	The complexity of error metrics. Inf. Process. Lett. Oliver Keszöcze, Mathias Soeken, Rolf Drechsler
2018	—	`conf`	Towards Automated Refinement of TLM Properties to RTL. MBMV Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2018	—	`conf`	Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws. ISVLSI Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler
2018	C	`conf`	Towards Reversed Approximate Hardware Design. DSD Saman Fröhlich, Daniel Große, Rolf Drechsler
2018	—	`conf`	Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation. IVSW Rolf Drechsler, Christoph Lüth, Görschwin Fey, Tim Güneysu
2018	A	`conf`	Towards fully automated TLM-to-RTL property refinement. DATE Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2017	J	`jnl`	A PLiM Computer for the Internet of Things. Computer Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli
2017	J	`jnl`	An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs. J. Low Power Electron. Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
2017	A	`conf`	An adaptive prioritized GECCO Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
2017	C	`conf`	Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata. ICCD Mehran Goli, Jannis Stoppe, Rolf Drechsler
2017	A	`conf`	Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications. DATE Mehran Goli, Jannis Stoppe, Rolf Drechsler
2017	—	`conf`	BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips. ISVLSI Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler
2017	A	`conf`	Data flow testing for virtual prototypes. DATE Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler
2017	A	`conf`	Dedicated synthesis for MZI-based optical circuits based on AND-inverter graphs. ICCAD Arighna Deb, Robert Wille, Rolf Drechsler
2017	A	`conf`	Early SoC security validation by VP-based static information flow analysis. ICCAD Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2017	A	`conf`	Effects of cell shapes on the routability of Digital Microfluidic Biochips. DATE Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
2017	C	`conf`	Efficient Construction of QMDDs for Irreversible, Reversible, and Quantum Functions. RC Philipp Niemann, Alwin Zulehner, Robert Wille, Rolf Drechsler
2017	—	`conf`	Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips. MBMV Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
2017	A	`conf`	Endurance management for resistive Logic-In-Memory computing architectures. DATE Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler
2017	—	`conf`	Enhancing robustness of sequential circuits using application-specific knowledge and formal methods. ASP-DAC Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler
2017	—	`conf`	Error Bounded Exact BDD Minimization in Approximate Computing. ISMVL Saman Fröhlich, Daniel Große, Rolf Drechsler
2017	—	`conf`	Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates. ISMVL Abhoy Kole, P. Mercy Nesa Rani, Kamalika Datta, Indranil Sengupta, Rolf Drechsler
2017	—	`conf`	Exact routing for micro-electrode-dot-array digital microfluidic biochips. ASP-DAC Oliver Keszöcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
2017	—	`conf`	Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing. MBMV Saman Fröhlich, Daniel Große, Rolf Drechsler
2017	—	`conf`	Extensions to the Reversible Hardware Description Language SyReC. ISMVL Zaid Al-Wardi, Robert Wille, Rolf Drechsler
2017	B	`conf`	Foreword. ETS Maria K. Michael, Rolf Drechsler, Stephan Eggersglüß, Haralampos-G. D. Stratigopoulos, Sybille Hellebrand, Rob Aitken
2017	—	`conf`	Identification of Efficient Clustering Techniques for Test Power Activity on the Layout. ATS Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
2017	—	`conf`	Machine learning based test pattern analysis for localizing critical power activity areas. DFT Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler
2017	—	`ed.`	Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017. MBMV Daniel Große, Rolf Drechsler
2017	C	`conf`	More than true or false: native support of irregular values in the automatic validation & verification of UML/OCL models. MEMOCODE Nils Przigoda, Philipp Niemann, Judith Peters, Frank Hilken, Robert Wille, Rolf Drechsler
2017	—	`conf`	OR-Inverter Graphs for the Synthesis of Optical Circuits. ISMVL Arighna Deb, Robert Wille, Rolf Drechsler
2017	J	`jnl`	On the Difficulty of Inserting Trojans in Reversible Computing Architectures. CoRR Xiaotong Cui, Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler, Kaijie Wu, Ramesh Karri
2017	A	`conf`	Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. DATE Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
2017	—	`conf`	ProACt: A Processor for High Performance On-demand Approximate Computing. ACM Great Lakes Symposium on VLSI Arun Chandrasekharan, Daniel Große, Rolf Drechsler
2017	—	`conf`	Reconfigurable TAP controllers with embedded compression for large test data volume. DFT Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler
2017	—	`conf`	Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements. SSCI Sebastian Huhn, Heike Sonnenberg, Stephan Eggersglüß, Brigitte Clausen, Rolf Drechsler
2017	—	`conf`	Semi-formal Cycle-Accurate Temporal Execution Traces Reconstruction. FORMATS Rehab Massoud, Jannis Stoppe, Daniel Große, Rolf Drechsler
2017	J	`jnl`	Synthesis of optical circuits using binary decision diagrams. Integr. Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler
2017	—	`conf`	Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach. FDL (Selected Papers) Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2017	J	`jnl`	Towards Reverse Engineering Reversible Logic. CoRR Samah Mohamed Saeed, Xiaotong Cui, Robert Wille, Alwin Zulehner, Kaijie Wu, Rolf Drechsler, Ramesh Karri
2017	C	`conf`	Towards VHDL-Based Design of Reversible Circuits - Work in Progress Report. RC Zaid Al-Wardi, Robert Wille, Rolf Drechsler
2017	J	`jnl`	Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pablo González de Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, Pablo Sánchez Espeso
2017	C	`conf`	Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. FDL Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2017	—	`conf`	Towards lightweight satisfiability solvers for self-verification. ISED Fritjof Bornebusch, Robert Wille, Rolf Drechsler
2017	—	`conf`	Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs. ASP-DAC Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler
2017	—	`conf`	Unintrusive aging analysis based on offline learning. DFT Frank Sill Torres, Pedro Fausto Rodrigues Leite, Rolf Drechsler
2017	C	`conf`	Yise - a novel framework for boolean networks using y-inverter graphs. MEMOCODE Arun Chandrasekharan, Daniel Große, Rolf Drechsler
2017	J	`jnl`	metaSMT: focus on your application and not on solver integration. Int. J. Softw. Tools Technol. Transf. Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey
2016	C	`ed.`	2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016 FDL Rolf Drechsler, Robert Wille
2016	C	`conf`	AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration. ICCD Mehran Goli, Jannis Stoppe, Rolf Drechsler
2016	A*	`conf`	An MIG-based compiler for programmable logic-in-memory architectures. DAC Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli
2016	—	`conf`	An improved gate library for logic synthesis of optical circuits. ISED Shuchishman Burman, Kamalika Datta, Robert Wille, Indranil Sengupta, Rolf Drechsler
2016	J	`jnl`	Analyzing Inconsistencies in UML/OCL Models. J. Circuits Syst. Comput. Nils Przigoda, Robert Wille, Rolf Drechsler
2016	J	`jnl`	Ancilla-free synthesis of large reversible functions using binary decision diagrams. J. Symb. Comput. Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
2016	—	`conf`	Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm. GECCO (Companion) Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
2016	A	`conf`	Approximation-aware rewriting of AIGs for error tolerant applications. ICCAD Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
2016	—	`conf`	BDD minimization for approximate computing. ASP-DAC Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler
2016	C	`conf`	Change impact analysis for hardware designs from natural language to system level. FDL Martin Ring, Jannis Stoppe, Christoph Lüth, Rolf Drechsler
2016	C	`conf`	Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models. MEMOCODE Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler
2016	A	`conf`	Compiled symbolic simulation for systemC. ICCAD Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2016	J	`jnl`	Complexity of reversible circuits and their quantum implementations. Theor. Comput. Sci. Nabila Abdessaied, Matthew Amy, Rolf Drechsler, Mathias Soeken
2016	J	`jnl`	Embedding of Large Boolean Functions for Reversible Logic. ACM J. Emerg. Technol. Comput. Syst. Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
2016	B	`conf`	Equivalence checking using Gröbner bases. FMCAD Amr A. R. Sayed-Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler
2016	—	`conf`	Exploring superior structural materials using multi-objective optimization and formal techniques. ISED Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler
2016	A	`conf`	Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs. DATE Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
2016	—	`conf`	Fault Detection in Parity Preserving Reversible Circuits. ISMVL Nils Przigoda, Gerhard W. Dueck, Robert Wille, Rolf Drechsler
2016	A	`conf`	Formal verification of integer multipliers by combining Gröbner basis with logic reduction. DATE Amr A. R. Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
2016	C	`conf`	Frame conditions in symbolic representations of UML/OCL models. MEMOCODE Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler
2016	A	`conf`	From biochips to quantum circuits: computer-aided design for emerging technologies. ICCAD Robert Wille, Bing Li, Ulf Schlichtmann, Rolf Drechsler
2016	—	`conf`	From reversible logic to quantum circuits: Logic design for an emerging technology. SAMOS Robert Wille, Anupam Chattopadhyay, Rolf Drechsler
2016	J	`jnl`	Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits. ACM J. Emerg. Technol. Comput. Syst. Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler
2016	—	`conf`	Generating and checking control logic in the HDL-based design of reversible circuits. ISED Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
2016	A	`conf`	Ground setting properties for an efficient translation of OCL in SMT-based model finding. MoDELS Nils Przigoda, Robert Wille, Rolf Drechsler
2016	C	`conf`	Guided lightweight Software test qualification for IP integration using Virtual Prototypes. ICCD Daniel Große, Hoang M. Le, Muhammad Hassan, Rolf Drechsler
2016	Misc	`conf`	Hardware/Software Co-Visualization on the Electronic System Level Using SystemC. VLSID Rolf Drechsler, Jannis Stoppe
2016	Misc	`conf`	Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library. VLSID Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
2016	C	`conf`	Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs - Work in Progress Report. RC Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
2016	—	`conf`	Integrating an SMT-Based ModelFinder into USE. MoDeVVa@MoDELS Nils Przigoda, Frank Hilken, Judith Peters, Robert Wille, Martin Gogolla, Rolf Drechsler
2016	—	`conf`	Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits. ASP-DAC Robert Wille, Oliver Keszöcze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler
2016	—	`conf`	Model-Based Specification and Refinement for Cyber-Physical Systems. LDIC Rolf Drechsler, Serge Autexier, Christoph Lüth
2016	C	`conf`	Multi-objective BDD optimization for RRAM based circuit design. DDECS Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
2016	—	`conf`	Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation. ISMVL Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
2016	J	`jnl`	On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
2016	C	`conf`	On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. FDL Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2016	—	`conf`	ParCoSS: Efficient Parallelized Compiled Symbolic Simulation. CAV (2) Vladimir Herdt, Hoang Minh Le, Daniel Große, Rolf Drechsler
2016	A*	`conf`	Precise error determination of approximated components in sequential circuits with model checking. DAC Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
2016	J	`jnl`	QMDDs: Efficient Quantum Function Representation and Manipulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler
2016	A	`conf`	Quantitative timing analysis of UML activity diagrams using statistical model checking. DATE Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, Rolf Drechsler
2016	—	`conf`	Re-Writing HDL Descriptions for Line-Aware Synthesis of Reversible Circuits. ISMVL Zaid Al-Wardi, Robert Wille, Rolf Drechsler
2016	J	`jnl`	Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability. ACM J. Emerg. Technol. Comput. Syst. Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya
2016	J	`jnl`	SyReC: A hardware description language for the specification and synthesis of reversible circuits. Integr. Robert Wille, Eleonora Schönborn, Mathias Soeken, Rolf Drechsler
2016	—	`conf`	Symbolic Error Metric Determination for Approximate Computing. MBMV Arun Chandrasekharan, Daniel Große, Mathias Soeken, Rolf Drechsler
2016	—	`conf`	Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits. ISMVL Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler
2016	—	`conf`	Towards a model-based verification methodology for Complex Swarm Systems (Invited paper). ISED Jonas Gomes Filho, Nils Przigoda, Robert Wille, Rolf Drechsler
2016	A	`conf`	Towards formal verification of real-world SystemC TLM peripheral models - a case study. DATE Hoang Minh Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
2016	B	`conf`	VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers. ETS Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler
2016	J	`jnl`	Verifying the structure and behavior in UML/OCL models using satisfiability solvers. IET Cyper-Phys. Syst.: Theory & Appl. Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler
2015	A	`conf`	A General and Exact Routing Methodology for Digital Microfluidic Biochips. ICCAD Oliver Keszöcze, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
2015	A*	`conf`	A generic representation of CCSL time constraints for UML/MARTE models. DAC Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler
2015	—	`conf`	An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization. ISMVL Arighna Deb, Robert Wille, Rolf Drechsler, Debesh K. Das
2015	—	`conf`	An Examination of the NCV-\|u1 > Quantum Library Based on Minimal Circuits. ISMVL Arman Allahyari-Abhari, Robert Wille, Rolf Drechsler
2015	J	`jnl`	Analyzing SystemC Designs: SystemC Analysis Approaches for Varying Applications. Sensors Jannis Stoppe, Rolf Drechsler
2015	—	`conf`	Analyzing and Simulating Time Descriptions from UML/MARTE CCSL. SyDe Summer School Judith Peters, Rolf Drechsler
2015	A	`conf`	Automated feature localization for dynamically generated SystemC designs. DATE Jannis Stoppe, Robert Wille, Rolf Drechsler
2015	Misc	`conf`	BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits. VLSID Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
2015	—	`conf`	Behavior Driven Development for Tests and Verification. SyDe Summer School Melanie Diepenbeck, Rolf Drechsler
2015	J	`jnl`	Benefits of illustrations and videos for technical documentations. Comput. Hum. Behav. Cornelia S. Große, Lisa Jungmann, Rolf Drechsler
2015	A	`conf`	Checking concurrent behavior in UML/OCL models. MoDELS Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, Rolf Drechsler
2015	C	`conf`	Contradiction Analysis for Inconsistent Formal Models. DDECS Nils Przigoda, Robert Wille, Rolf Drechsler
2015	—	`conf`	Coverage of OCL Operation Specifications and Invariants. TAP@STAF Mathias Soeken, Julia Seiter, Rolf Drechsler
2015	—	`conf`	Design and Synthesis of Reversible Circuits using Hardware Description Languages. SyDe Summer School Eleonora Schönborn, Rolf Drechsler
2015	—	`conf`	Determining the minimal number of swap gates for multi-dimensional nearest neighbor quantum circuits. ASP-DAC Aaron Lye, Robert Wille, Rolf Drechsler
2015	—	`conf`	Development of Consistent Formal Models. SyDe Summer School Julia Seiter, Rolf Drechsler
2015	C	`conf`	Ensuring safety and reliability of IP-based system design - A container approach. RSP Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, Rolf Drechsler
2015	—	`conf`	Envisioning self-verification of electronic systems. ReCoSoC Rolf Drechsler, Martin Fränzle, Robert Wille
2015	A	`conf`	Formal Methods for Emerging Technologies. ICCAD Robert Wille, Rolf Drechsler
2015	—	`ed.`	Formal Modeling and Verification of Cyber-Physical Systems, 1st International Summer School on Methods and Tools for the Design of Digital Systems, Bremen, Germany, September 2015 SyDe Summer School Rolf Drechsler, Ulrich Kühne
2015	—	`book`	Formal Specification Level - Concepts, Methods, and Algorithms. Mathias Soeken, Rolf Drechsler
2015	J	`jnl`	Incorporating user preferences in many-objective optimization using relation ε-preferred. Nat. Comput. Nicole Drechsler, André Sülflow, Rolf Drechsler
2015	B	`conf`	Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules. ATVA Vladimir Herdt, Hoang Minh Le, Daniel Große, Rolf Drechsler
2015	C	`conf`	Leveraging the Analysis for Invariant Independence in Formal System Models. DSD Nils Przigoda, Robert Wille, Rolf Drechsler
2015	A	`conf`	Multi-Objective BDD Optimization with Evolutionary Algorithms. GECCO Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
2015	—	`conf`	Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits. ISVLSI Amr A. R. Sayed-Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler
2015	C	`conf`	Requirement Phrasing Assistance Using Automatic Quality Assessment. DDECS Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler
2015	—	`conf`	Reverse BDD-based synthesis for splitter-free optical circuits. ASP-DAC Robert Wille, Oliver Keszöcze, Clemens Hopfmuller, Rolf Drechsler
2015	C	`conf`	Reversible circuit rewriting with simulated annealing. VLSI-SoC Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler
2015	—	`conf`	Reversible computation. IGSC Rolf Drechsler, Robert Wille
2015	J	`jnl`	Scalable One-Pass Synthesis for Digital Microfluidic Biochips. IEEE Des. Test Robert Wille, Oliver Keszöcze, Rolf Drechsler, Tobias Boehnisch, Alexander Kroker
2015	B	`conf`	Simulation Graphs for Reverse Engineering. FMCAD Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton
2015	C	`conf`	Technology Mapping for Single Target Gate Based Circuits Using Boolean Functional Decomposition. RC Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
2015	C	`conf`	Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits. RC Zaid Al-Wardi, Robert Wille, Rolf Drechsler
2015	—	`conf`	Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses. MoDeVVa@MoDELS Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler
2015	—	`conf`	Verbesserung der Fehlersuche in inkonsistenten formalen Modellen (Erweiterte Zusammenfassung). MBMV Nils Przigoda, Robert Wille, Rolf Drechsler
2015	C	`conf`	Verification-Driven Design Across Abstraction Levels: A Case Study. DSD Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler
2015	A*	`conf`	Verifying SystemC using stateful symbolic simulation. DAC Vladimir Herdt, Hoang Minh Le, Rolf Drechsler
2014	—	`conf`	A Cube Pairing Approach for Synthesis of ESOP-Based Reversible Circuit. ISMVL Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler
2014	—	`conf`	A Logic for Cardinality Constraints (Extended Abstract). MBMV Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey
2014	J	`jnl`	A framework for reversible circuit complexity. CoRR Mathias Soeken, Nabila Abdessaied, Rolf Drechsler
2014	J	`jnl`	An Approach to Reversible Logic Synthesis Using Input and Output Permutations. Trans. Comput. Sci. Kamalika Datta, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
2014	J	`jnl`	An effective fault ordering heuristic for SAT-based dynamic test compaction techniques. it Inf. Technol. Stephan Eggersglüß, Rolf Drechsler
2014	J	`jnl`	Ancilla-free synthesis of large reversible functions using binary decision diagrams. CoRR Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
2014	—	`ed.`	Aspekte der Technischen Informatik - Festschrift zum 60. Geburtstag von Bernd Becker. Aspekte der Technischen Informatik Rolf Drechsler
2014	A	`conf`	Automated and quality-driven requirements engineering. ICCAD Rolf Drechsler, Mathias Soeken, Robert Wille
2014	C	`conf`	Automatic refinement checking for formal system models. FDL Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
2014	C	`conf`	Automating the translation of assertions using natural language processing techniques. FDL Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris, Rolf Drechsler
2014	—	`conf`	Behaviour Driven Development for Tests and Verification. TAP@STAF Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
2014	J	`jnl`	Considering nearest neighbor constraints of quantum circuits at the reversible circuit level. Quantum Inf. Process. Robert Wille, Aaron Lye, Rolf Drechsler
2014	—	`conf`	Der h2-lndex: Zur vermessenen Vermessung der wissenschaftlichen Welt. Aspekte der Technischen Informatik Marc Herbstritt, Rolf Drechsler
2014	—	`conf`	Determining Cases of Scenarios to Improve Coverage in Simulation-based Verification. SBCCI Shuo Yang, Robert Wille, Rolf Drechsler
2014	—	`conf`	Efficient synthesis of quantum circuits implementing clifford group operations. ASP-DAC Philipp Niemann, Robert Wille, Rolf Drechsler
2014	J	`jnl`	Embedding of Large Boolean Functions for Reversible Logic. CoRR Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
2014	C	`conf`	Equivalence Checking in Multi-level Quantum Systems. RC Philipp Niemann, Robert Wille, Rolf Drechsler
2014	A*	`conf`	Exact One-pass Synthesis of Digital Microfluidic Biochips. DAC Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler
2014	J	`jnl`	Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Robert Wille, Aaron Lye, Rolf Drechsler
2014	A	`conf`	Exact routing for digital microfluidic biochips with temporary blockages. ICCAD Oliver Keszöcze, Robert Wille, Rolf Drechsler
2014	—	`conf`	Formale Methoden für Alle. MBMV Mathias Soeken, Max Nitze, Rolf Drechsler
2014	—	`conf`	Funktionale Abdeckungsanalyse von C-Programmen. MBMV Aljoscha Windhorst, Hoang Minh Le, Daniel Große, Rolf Drechsler
2014	B	`conf`	Generating SystemC Implementations for Clock Constraints Specified in UML/MARTE CCSL. ICECCS Judith Peters, Robert Wille, Rolf Drechsler
2014	J	`jnl`	Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic. Trans. Comput. Sci. Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler
2014	C	`conf`	Improving Coverage of Simulation-Based Verification by Dedicated Stimuli Generation. DSD Shuo Yang, Robert Wille, Rolf Drechsler
2014	J	`jnl`	Introduction to the Special Issue on Reversible Computation. ACM J. Emerg. Technol. Comput. Syst. Robert Wille, Rolf Drechsler, Mehdi Baradaran Tahoori
2014	C	`conf`	Mapping NCV Circuits to Optimized Clifford+T Circuits. RC D. Michael Miller, Mathias Soeken, Rolf Drechsler
2014	C	`conf`	MetaSMT: a unified interface to SMT-LIB2. FDL Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler
2014	—	`conf`	Optimal SWAP gate insertion for nearest neighbor quantum circuits. ASP-DAC Robert Wille, Aaron Lye, Rolf Drechsler
2014	B	`conf`	Optimization-based multiple target test generation for highly compacted test sets. ETS Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
2014	C	`conf`	Optimizing DD-based synthesis of reversible circuits using negative control lines. DDECS Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
2014	A	`conf`	Panel: Future SoC verification methodology: UVM evolution or revolution? DATE Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan J. Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev
2014	C	`conf`	Quantum Circuit Optimization by Hadamard Gate Reduction. RC Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
2014	—	`conf`	Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization. DTIS Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer
2014	—	`conf`	Requirements Engineering for Cyber-Physical Systems - Challenges in the Context of "Industrie 4.0". APMS (1) Stefan A. Wiesner, Christian Gorldt, Mathias Soeken, Klaus-Dieter Thoben, Rolf Drechsler
2014	C	`conf`	RevVis: Visualization of Structures and Properties in Reversible Circuits. RC Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler
2014	—	`conf`	Safe IP Integration Using Container Modules. ISED Rolf Drechsler, Ulrich Kühne
2014	A*	`conf`	Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. DAC Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Grüttner, Thomas Kruse, Christoph Kuznik, Hoang Minh Le, Andreas Mauderer, Wolfgang Müller, Daniel Müller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, S. Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl
2014	—	`conf`	Self-Verification as the Key Technology for Next Generation Electronic Systems. SBCCI Rolf Drechsler, Hoang Minh Le, Mathias Soeken
2014	J	`jnl`	Testing integrated circuits. it Inf. Technol. Rolf Drechsler
2014	A	`conf`	Towards verifying determinism of SystemC designs. DATE Hoang Minh Le, Rolf Drechsler
2014	J	`jnl`	Trading off circuit lines and gate costs in the synthesis of reversible logic. Integr. Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler
2014	J	`jnl`	Upper bounds for reversible circuits based on Young subgroups. Inf. Process. Lett. Nabila Abdessaied, Mathias Soeken, Michael Kirkedal Thomsen, Rolf Drechsler
2014	—	`conf`	Validating SystemC Implementations Against Their Formal Specifications. SBCCI Jannis Stoppe, Robert Wille, Rolf Drechsler
2014	C	`conf`	Verifying consistency between activity diagrams and their corresponding OCL contracts. FDL Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
2014	—	`conf`	iTac: Aspect Based Sentiment Analysis using Sentiment Trees and Dictionaries. SemEval@COLING Fritjof Bornebusch, Glaucia Cancino, Melanie Diepenbeck, Rolf Drechsler, Smith Djomkam, Alvine Nzeungang Fanseu, Maryam Jalali, Marc Michael, Jamal Mohsen, Max Nitze, Christina Plump, Mathias Soeken, Hubert Fred Tchambo, Toni, Henning Ziegler
2013	—	`conf`	A compact and efficient SAT encoding for quantum circuits. AFRICON Robert Wille, Nils Przigoda, Rolf Drechsler
2013	J	`jnl`	A formal model for embedded brain reading. Ind. Robot Elsa Andrea Kirchner, Rolf Drechsler
2013	—	`conf`	An evolutionary approach to reversible logic synthesis using output permutation. IDT Kamalika Datta, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
2013	C	`conf`	Cone of Influence Analysis at the Electronic System Level Using Machine Learning. DSD Jannis Stoppe, Robert Wille, Rolf Drechsler
2013	—	`conf`	Data extraction from SystemC designs using debug symbols and the SystemC API. ISVLSI Jannis Stoppe, Robert Wille, Rolf Drechsler
2013	—	`conf`	Debugging of Reversible Circuits Using pDDs. ISMVL Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler
2013	A	`conf`	Determining relevant model elements for the verification of UML/OCL specifications. DATE Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler
2013	J	`jnl`	Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits. J. Multiple Valued Log. Soft Comput. Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
2013	J	`jnl`	Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. Daniel Große, Görschwin Fey, Rolf Drechsler
2013	—	`conf`	Exact Template Matching Using Boolean Satisfiability. ISMVL Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler
2013	C	`conf`	Exploiting Negative Control Lines in the Optimization of Reversible Circuits. RC Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
2013	—	`conf`	Exploiting reversibility in the complete simulation of reversible circuits. AFRICON Robert Wille, Simon Stelter, Rolf Drechsler
2013	—	`conf`	Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits. ISMVL Robert Wille, Hongyan Zhang, Rolf Drechsler
2013	—	`conf`	Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen. MBMV Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler
2013	—	`conf`	Grammar-based program generation based on model finding. IDT Mathias Soeken, Rolf Drechsler
2013	C	`conf`	Hardware-Software Co-Visualization: Developing systems in the holodeck. DDECS Rolf Drechsler, Mathias Soeken
2013	A	`conf`	Improved SAT-based ATPG: more constraints, better compaction. ICCAD Stephan Eggersglüß, Robert Wille, Rolf Drechsler
2013	—	`conf`	Improving the mapping of reversible circuits to quantum circuits using multiple target lines. ASP-DAC Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler
2013	C	`conf`	Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred. IJCCI Nicole Drechsler, André Sülflow, Rolf Drechsler
2013	C	`conf`	Minimal Stimuli Generation in Simulation-Based Verification. DSD Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler
2013	J	`jnl`	On quantum circuits employing roots of the Pauli matrices. CoRR Mathias Soeken, D. Michael Miller, Rolf Drechsler
2013	C	`conf`	On the "Q" in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-Structure. RC Philipp Niemann, Robert Wille, Rolf Drechsler
2013	—	`conf`	PASSAT 2.0: A multi-functional SAT-based testing framework. LATW Rolf Drechsler, Melanie Diepenbeck, Stephan Eggersglüß, Robert Wille
2013	C	`conf`	Reducing the Depth of Quantum Circuits Using Additional Circuit Lines. RC Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler
2013	C	`conf`	Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure. RC Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler
2013	A	`conf`	Scalable fault localization for SystemC TLM designs. DATE Hoang Minh Le, Daniel Große, Rolf Drechsler
2013	—	`conf`	Text statt C++: Automatisierung des Systementwurfs mit Hilfe natürlicher Sprachverarbeitung. GI-Jahrestagung Rolf Drechsler, Mathias Soeken, Robert Wille
2013	—	`conf`	The SyReC hardware description language: Enabling scalable synthesis of reversible circuits. MWSCAS Robert Wille, Rolf Drechsler
2013	A	`conf`	Towards a generic verification methodology for system models. DATE Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler
2013	—	`conf`	Towards automatic scenario generation from coverage information. AST@ICSE Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
2013	A*	`conf`	Verifying SystemC using an intermediate verification language and symbolic simulation. DAC Hoang Minh Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
2012	J	`jnl`	A Highly Fault-Efficient SAT-Based ATPG Flow. IEEE Des. Test Comput. Stephan Eggersglüß, Rolf Drechsler
2012	—	`conf`	A Synthesis Flow for Sequential Reversible Circuits. ISMVL Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler
2012	A	`conf`	A guiding coverage metric for formal verification. DATE Finn Haedicke, Daniel Große, Rolf Drechsler
2012	C	`conf`	A new SAT-based ATPG for generating highly compacted test sets. DDECS Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
2012	B	`ed.`	Applications of Evolutionary Computation - EvoApplications 2012: EvoCOMNET, EvoCOMPLEX, EvoFIN, EvoGAMES, EvoHOT, EvoIASP, EvoNUM, EvoPAR, EvoRISK, EvoSTIM, and EvoSTOC, Málaga, Spain, April 11-13, 2012, Proceedings EvoApplications Cecilia Di Chio, Alexandros Agapitos, Stefano Cagnoni, Carlos Cotta, Francisco Fernández de Vega, Gianni A. Di Caro, Rolf Drechsler, Anikó Ekárt, Anna Isabel Esparcia-Alcázar, Muddassar Farooq, William B. Langdon, Juan Julián Merelo Guervós, Mike Preuss, Hendrik Richter, Sara Silva, Anabela Simões, Giovanni Squillero, Ernesto Tarantino, Andrea Tettamanzi, Julian Togelius, Neil Urquhart, Sima Uyar, Georgios N. Yannakakis
2012	—	`conf`	Assisted Behavior Driven Development Using Natural Language Processing. TOOLS (50) Mathias Soeken, Robert Wille, Rolf Drechsler
2012	J	`jnl`	Automatic TLM Fault Localization for SystemC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hoang Minh Le, Daniel Große, Rolf Drechsler
2012	A	`conf`	Automatic design of low-power encoders using reversible circuit synthesis. DATE Robert Wille, Rolf Drechsler, Christof Osewold, Alberto García Ortiz
2012	—	`conf`	Behavior Driven Development for circuit design and verification. HLDVT Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
2012	—	`conf`	CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC. MBMV Finn Haedicke, Hoang Minh Le, Daniel Große, Rolf Drechsler
2012	—	`conf`	CRAVE: An advanced constrained random verification environment for SystemC. ISSoC Finn Haedicke, Hoang Minh Le, Daniel Große, Rolf Drechsler
2012	—	`conf`	Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic. ISVLSI Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler
2012	B	`conf`	Complete and effective robustness checking by means of interpolation. FMCAD Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav, Rolf Drechsler
2012	B	`conf`	Completeness-Driven Development. ICGT Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang Minh Le, Julia Seiter, Mathias Soeken, Robert Wille
2012	C	`conf`	Coverage-Driven Stimuli Generation. DSD Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler
2012	A	`conf`	Debugging of inconsistent UML/OCL models. DATE Robert Wille, Mathias Soeken, Rolf Drechsler
2012	A	`conf`	Eliminating invariants in UML/OCL models. DATE Mathias Soeken, Robert Wille, Rolf Drechsler
2012	J	`jnl`	Equivalence Checking of Reversible Circuits. J. Multiple Valued Log. Soft Comput. Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
2012	—	`conf`	Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines. ISMVL Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
2012	—	`conf`	FoREnSiC- An Automatic Debugging Environment for C Programs. Haifa Verification Conference Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
2012	J	`jnl`	Foreword: Special Issue on Reversible Computation. J. Multiple Valued Log. Soft Comput. Rolf Drechsler, Irek Ulidowski, Robert Wille
2012	—	`conf`	Formal Specification Level. FDL (Selected Papers) Rolf Drechsler, Mathias Soeken, Robert Wille
2012	C	`conf`	Formal Specification Level: Towards verification-driven design based on natural language processing. FDL Rolf Drechsler, Mathias Soeken, Robert Wille
2012	—	`conf`	From Requirements and Scenarios to ESL Design in SystemC. ISED Hoang M. Le, Daniel Große, Rolf Drechsler
2012	—	`conf`	Generating formal system models from natural language descriptions. HLDVT Rolf Drechsler, Ian G. Harris, Robert Wille
2012	—	`book`	High Quality Test Pattern Generation and Boolean Satisfiability. Stephan Eggersglüß, Rolf Drechsler
2012	C	`conf`	Localizing features of ESL models for design understanding. FDL Marc Michael, Daniel Große, Rolf Drechsler
2012	—	`conf`	Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits. ISMVL Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler
2012	C	`conf`	Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams. RC Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler
2012	J	`jnl`	Reducing Reversible Circuit Cost by Adding Lines. J. Multiple Valued Log. Soft Comput. D. Michael Miller, Robert Wille, Rolf Drechsler
2012	J	`jnl`	RevKit: A Toolkit for Reversible Circuit Design. J. Multiple Valued Log. Soft Comput. Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
2012	—	`conf`	Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology - (Invited Paper). VDAT Rolf Drechsler, Robert Wille
2012	—	`conf`	Synthesis of Reversible Circuits Using Decision Diagrams. ISED Rolf Drechsler, Robert Wille
2012	—	`conf`	Synthesis of reversible circuits with minimal lines for large functions. ASP-DAC Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
2012	Misc	`conf`	The system verification methodology for advanced TLM verification. CODES+ISSS Marcio Ferreira da Silva Oliveira, Christoph Kuznik, Hoang Minh Le, Daniel Große, Finn Haedicke, Wolfgang Müller, Rolf Drechsler, Wolfgang Ecker, Volkan Esen
2012	C	`conf`	Using RC Mathias Soeken, Robert Wille, Shin-ichi Minato, Rolf Drechsler
2011	—	`conf`	ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization. ISVLSI Robert Wille, Hongyan Zhang, Rolf Drechsler
2011	C	`conf`	Analyzing dependability measures at the Electronic System Level. FDL Marc Michael, Daniel Große, Rolf Drechsler
2011	—	`ed.`	Applications of Evolutionary Computation - EvoApplications 2011: EvoCOMNET, EvoFIN, EvoHOT, EvoMUSART, EvoSTIM, and EvoTRANSLOG, Torino, Italy, April 27-29, 2011, Proceedings, Part II EvoApplications (2) Cecilia Di Chio, Anthony Brabazon, Gianni A. Di Caro, Rolf Drechsler, Muddassar Farooq, Jörn Grahl, Gary Greenfield, Christian Prins, Juan Romero, Giovanni Squillero, Ernesto Tarantino, Andrea Tettamanzi, Neil Urquhart, A. Sima Etaner-Uyar
2011	A	`conf`	As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization. DATE Stephan Eggersglüß, Rolf Drechsler
2011	C	`conf`	Automatic property generation for the formal verification of bus bridges. DDECS Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
2011	J	`jnl`	Debugging reversible circuits. Integr. Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
2011	—	`conf`	Designing a RISC CPU in Reversible Logic. ISMVL Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
2011	—	`conf`	Designing a RISC CPU in Reversible Logic. MBMV Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
2011	—	`conf`	Determining minimal testsets for reversible circuits using Boolean satisfiability. AFRICON Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler
2011	A	`conf`	Determining the minimal number of lines for large reversible circuits. DATE Robert Wille, Oliver Keszöcze, Rolf Drechsler
2011	J	`jnl`	Effective Robustness Analysis Using Bounded Model Checking Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler
2011	J	`jnl`	Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Stephan Eggersglüß, Rolf Drechsler
2011	C	`conf`	Efficient realization of control logic in reversible circuits. FDL Sebastian Offermann, Robert Wille, Rolf Drechsler
2011	—	`conf`	Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models. TAP@TOOLS Mathias Soeken, Robert Wille, Rolf Drechsler
2011	—	`conf`	From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits. ISMVL Rolf Drechsler, Robert Wille
2011	—	`conf`	Improved Fault Diagnosis for Reversible Circuits. Asian Test Symposium Hongyan Zhang, Robert Wille, Rolf Drechsler
2011	—	`conf`	Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary Algorithms. EvoApplications (2) Rolf Drechsler, Alexander Finder, Robert Wille
2011	C	`conf`	RevKit: An Open Source Toolkit for the Design of Reversible Circuits. RC Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
2011	—	`conf`	Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction. MBMV Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
2011	—	`conf`	Simulation-based equivalence checking between SystemC models at different levels of abstraction. ACM Great Lakes Symposium on VLSI Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
2011	J	`jnl`	Synthesis of Quantum Circuits for Linear Nearest Neighbor Architectures. CoRR Mehdi Saeedi, Robert Wille, Rolf Drechsler
2011	J	`jnl`	Synthesis of quantum circuits for linear nearest neighbor architectures. Quantum Inf. Process. Mehdi Saeedi, Robert Wille, Rolf Drechsler
2011	C	`conf`	TLM protocol compliance checking at the Electronic System Level. DDECS Mohamed Bawadekji, Daniel Große, Rolf Drechsler
2011	—	`conf`	Towards Automatic Property Generation for the Formal Verification of Bus Bridges. MBMV Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
2011	—	`conf`	Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines. ISORC Workshops Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler
2011	—	`conf`	Towards automatic determination of problem bounds for object instantiation in static model verification. MoDeVVa@MoDELS Mathias Soeken, Robert Wille, Rolf Drechsler
2011	A	`conf`	Verifying dynamic aspects of UML models. DATE Mathias Soeken, Robert Wille, Rolf Drechsler
2011	—	`conf`	metaSMT: Focus on Your Application not on Solver Integration. DIFTS@FMCAD Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler
2010	C	`conf`	A better-than-worst-case robustness measure. DDECS Stefan Frehse, Görschwin Fey, Rolf Drechsler
2010	—	`conf`	An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions. ISMVL Alexander Finder, Rolf Drechsler
2010	—	`conf`	Automatic Fault Localization for Programmable Logic Controllers. FORMS/FORMAT André Sülflow, Rolf Drechsler
2010	—	`conf`	Automatic Fault Localization for SystemC TLM Designs. MTV Hoang Minh Le, Daniel Große, Rolf Drechsler
2010	J	`jnl`	Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). it Inf. Technol. Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler
2010	J	`jnl`	BDD-Based Synthesis of Reversible Logic. Int. J. Appl. Metaheuristic Comput. Robert Wille, Rolf Drechsler
2010	—	`book`	Debugging at the Electronic System Level. Frank Rogin, Rolf Drechsler
2010	—	`conf`	Efficient Simulation-Based Debugging of Reversible Logic. ISMVL Stefan Frehse, Robert Wille, Rolf Drechsler
2010	C	`conf`	Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation. ISCAS Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
2010	—	`conf`	Enhancing debugging of multiple missing control errors in reversible logic. ACM Great Lakes Symposium on VLSI Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
2010	C	`conf`	Formal verification meets robustness checking - Techniques and challenges. DDECS Rolf Drechsler, Görschwin Fey
2010	—	`conf`	Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition. IDT Mathias Soeken, Robert Wille, Rolf Drechsler
2010	B	`conf`	Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. ETS Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler
2010	J	`jnl`	Incremental Solving Techniques for SAT-based ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel Tille, Stephan Eggersglüß, Rolf Drechsler
2010	J	`jnl`	MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electron. Test. Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler
2010	A	`conf`	Polynomial datapath optimization using constraint solving and formal modelling. ICCAD Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler
2010	C	`conf`	Proving transaction and system-level properties of untimed SystemC TLM designs. MEMOCODE Daniel Große, Hoang Minh Le, Rolf Drechsler
2010	—	`book`	Quality-Driven SystemC Design Daniel Große, Rolf Drechsler
2010	—	`conf`	Reducing Reversible Circuit Cost by Adding Lines. ISMVL D. Michael Miller, Robert Wille, Rolf Drechsler
2010	A*	`conf`	Reducing the number of lines in reversible circuits. DAC Robert Wille, Mathias Soeken, Rolf Drechsler
2010	C	`conf`	RobuCheck: A Robustness Checker for Digital Circuits. DSD Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
2010	—	`conf`	RobuCheck: a robustness checker for digital circuits. DYADEM-FTS@EDCC Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
2010	—	`conf`	SAT-based ATPG for reversible circuits. IDT Hongyan Zhang, Robert Wille, Rolf Drechsler
2010	C	`conf`	SyReC: A Programming Language for Synthesis of Reversible Circuits. FDL Robert Wille, Sebastian Offermann, Rolf Drechsler
2010	—	`conf`	SyReC: A Programming Language for Synthesis of Reversible Circuits. MBMV Robert Wille, Sebastian Offermann, Rolf Drechsler
2010	J	`jnl`	Synthese reversibler Logik (Synthesizing Reversible Logic). it Inf. Technol. Robert Wille, Rolf Drechsler
2010	C	`conf`	Synthesizing multiplier in reversible logic. DDECS Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
2010	J	`jnl`	Towards Fully Automatic Synthesis of Embedded Software. IEEE Embed. Syst. Lett. Ulrich Kühne, Daniel Große, Rolf Drechsler
2010	—	`conf`	Towards Unifying Localization and Explanation for Automated Debugging. MTV Görschwin Fey, André Sülflow, Rolf Drechsler
2010	—	`book`	Towards a Design Flow for Reversible Logic. Robert Wille, Rolf Drechsler
2010	—	`conf`	Towards analyzing functional coverage in SystemC TLM property checking. HLDVT Hoang Minh Le, Daniel Große, Rolf Drechsler
2010	C	`conf`	Using QBF to increase accuracy of SAT-based debugging. ISCAS André Sülflow, Görschwin Fey, Rolf Drechsler
2010	—	`conf`	Verifying UML/OCL Models Using Boolean Satisfiability. MBMV Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
2010	A	`conf`	Verifying UML/OCL models using Boolean satisfiability. DATE Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
2010	C	`conf`	Window optimization of reversible and quantum circuits. DDECS Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
2009	—	`conf`	09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers. Algorithms and Applications for Next Generation SAT Solvers Bernd Becker, Valeria Bertacco, Rolf Drechsler, Masahiro Fujita
2009	C	`conf`	A fast untestability proof for SAT-based ATPG. DDECS Daniel Tille, Rolf Drechsler
2009	J	`jnl`	Advanced verification by automatic property generation. IET Comput. Digit. Tech. Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
2009	—	`ed.`	Algorithms and Applications for Next Generation SAT Solvers, 08.11. - 13.11.2009 Algorithms and Applications for Next Generation SAT Solvers Bernd Becker, V. Bertacoo, Rolf Drechsler, Masahiro Fujita
2009	C	`conf`	Approximate BDD Minimization by Weighted A. ISCAS Rüdiger Ebendt, Rolf Drechsler
2009	—	`conf`	Automatic debugging of System-on-a-Chip designs. SoCC Frank Rogin, Rolf Drechsler, Steffen Rülke
2009	A*	`conf`	BDD-based synthesis of reversible logic for large functions. DAC Robert Wille, Rolf Drechsler
2009	A*	`conf`	Computing bounds for fault tolerance using formal techniques. DAC Görschwin Fey, André Sülflow, Rolf Drechsler
2009	—	`conf`	Contradictory antecedent debugging in bounded model checking. ACM Great Lakes Symposium on VLSI Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
2009	A	`conf`	Debugging of Toffoli networks. DATE Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
2009	—	`conf`	Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic. RC@ETAPS Robert Wille, Rolf Drechsler
2009	J	`jnl`	Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it Inf. Technol. Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
2009	—	`conf`	Equivalence Checking of Reversible Circuits. ISMVL Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
2009	—	`conf`	Equivalence Checking of Reversible Circuits. MBMV Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
2009	—	`conf`	Evaluation of Cardinality Constraints on SMT-Based Debugging. ISMVL André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler
2009	J	`jnl`	Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
2009	J	`jnl`	Exact Synthesis of Elementary Quantum Gate Circuits. J. Multiple Valued Log. Soft Comput. Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
2009	—	`conf`	Formal Verification of Abstract SystemC Models. Algorithms and Applications for Next Generation SAT Solvers Daniel Große, Hoang Minh Le, Rolf Drechsler
2009	B	`conf`	Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. ETS Stephan Eggersglüß, Rolf Drechsler
2009	—	`conf`	Increasing the Accuracy of SAT-based Debugging. MBMV André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
2009	A	`conf`	Increasing the accuracy of SAT-based debugging. DATE André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
2009	—	`conf`	Induction-Based Formal Verification of SystemC TLM Designs. MTV Daniel Große, Hoang Minh Le, Rolf Drechsler
2009	—	`ch.`	Non-Clausal SAT and ATPG. Handbook of Satisfiability Rolf Drechsler, Tommi A. Junttila, Ilkka Niemelä
2009	A	`conf`	Overcoming limitations of the SystemC data introspection. DATE Christian Genz, Rolf Drechsler
2009	A	`conf`	Property analysis and design understanding. DATE Ulrich Kühne, Daniel Große, Rolf Drechsler
2009	Misc	`conf`	Reversible Logic Synthesis with Output Permutation. VLSI Design Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
2009	C	`conf`	Robustness Check for Multiple Faults Using Formal Techniques. DSD Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
2009	C	`conf`	SMT-based stimuli generation in the SystemC Verification library. FDL Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
2009	—	`conf`	SWORD - Module-based SAT Solving. Algorithms and Applications for Next Generation SAT Solvers Robert Wille, Jean Christoph Jung, André Sülflow, Rolf Drechsler
2009	—	`conf`	Speeding up SAT-Based ATPG Using Dynamic Clause Activation. Asian Test Symposium Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
2009	—	`book`	Test Pattern Generation using Boolean Proof Engines. Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille
2009	A	`conf`	Timing Arc based logic analysis for false noise reduction. ICCAD Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler
2009	—	`conf`	Using a two-dimensional fault list for compact Automatic Test Pattern Generation. LATW Marc Messing, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
2009	J	`jnl`	Weighted A Artif. Intell. Rüdiger Ebendt, Rolf Drechsler
2009	C	`conf`	WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
2008	—	`conf`	A Basis for Formal Robustness Checking. ISQED Görschwin Fey, Rolf Drechsler
2008	—	`conf`	Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. ISQED Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
2008	J	`jnl`	Analyzing Functional Coverage in Bounded Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel Große, Ulrich Kühne, Rolf Drechsler
2008	—	`ed.`	Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings EvoWorkshops Mario Giacobini, Anthony Brabazon, Stefano Cagnoni, Gianni Di Caro, Rolf Drechsler, Anikó Ekárt, Anna Esparcia-Alcázar, Muddassar Farooq, Andreas Fink, Jon McCormack, Michael O'Neill, Juan Romero, Franz Rothlauf, Giovanni Squillero, Sima Uyar, Shengxiang Yang
2008	J	`jnl`	Automatic Fault Localization for Property Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler
2008	A	`conf`	Automatic Generation of Complex Properties for Hardware Designs. DATE Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
2008	—	`conf`	Comparative Study by Solving the Test Compaction Problem. ISMVL Doina Logofatu, Rolf Drechsler
2008	C	`conf`	Contradiction Analysis for Constraint-based Random Simulation. FDL Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
2008	—	`conf`	Debugging Contradictory Constraints in Constraint-Based Random Simulation. FDL (Selected Papers) Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
2008	—	`conf`	Debugging Design Errors by Using Unsatisfiable Cores. MBMV André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
2008	—	`conf`	Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
2008	C	`conf`	Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. DSD Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler
2008	J	`jnl`	Improved SAT-based Reachability Analysis with Observability Don't Cares. J. Satisf. Boolean Model. Comput. Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
2008	C	`conf`	Incremental SAT Instance Generation for SAT-based ATPG. DDECS Daniel Tille, Rolf Drechsler
2008	J	`jnl`	Logic Minimization and Testability of 2-SPP Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa
2008	J	`jnl`	Modeling and proving functional completeness in formal verification of counting heads. Int. J. Softw. Tools Technol. Transf. Sebastian Kinder, Rolf Drechsler
2008	J	`jnl`	On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille
2008	—	`conf`	On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. ISMVL Stephan Eggersglüß, Rolf Drechsler
2008	J	`jnl`	On the construction of small fully testable circuits with low depth. Microprocess. Microsystems Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
2008	C	`conf`	Process variations aware robust on-chip bus architecture synthesis for MPSoCs. ISCAS Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner
2008	—	`conf`	Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow. MTV Ulrich Kühne, Daniel Große, Rolf Drechsler
2008	—	`conf`	RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler
2008	—	`conf`	Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival. ASP-DAC Sujan Pandey, Rolf Drechsler
2008	—	`book`	Robustness and usability in modern design flows. Görschwin Fey, Rolf Drechsler
2008	—	`conf`	SAT-based Automatic Test Pattern Generation. Evolutionary Test Generation Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille
2008	A	`conf`	Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. DATE Sujan Pandey, Rolf Drechsler
2008	—	`conf`	Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking. MBMV Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
2008	—	`conf`	Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. ISVLSI Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler
2008	—	`conf`	Using unsatisfiable cores to debug multiple design errors. ACM Great Lakes Symposium on VLSI André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
2007	C	`conf`	An Integrated SystemC Debugging Environment. FDL Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke
2007	—	`ed.`	Applications of Evolutinary Computing, EvoWorkshops 2007: EvoCoMnet, EvoFIN, EvoIASP,EvoINTERACTION, EvoMUSART, EvoSTOC and EvoTransLog, Valencia, Spain, April11-13, 2007, Proceedings. EvoWorkshops Mario Giacobini, Anthony Brabazon, Stefano Cagnoni, Gianni Di Caro, Rolf Drechsler, Muddassar Farooq, Andreas Fink, Evelyne Lutton, Penousal Machado, Stefan Minner, Michael O'Neill, Juan Romero, Franz Rothlauf, Giovanni Squillero, Hideyuki Takagi, Sima Uyar, Shengxiang Yang
2007	C	`conf`	Co-synthesis of custom on-chip bus and memory for MPSoC architectures. VLSI-SoC Sujan Pandey, Christian Genz, Rolf Drechsler
2007	C	`conf`	Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
2007	A	`conf`	Estimating functional coverage in bounded model checking. DATE Daniel Große, Ulrich Kühne, Rolf Drechsler
2007	—	`conf`	Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. ISMVL Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler
2007	—	`conf`	Exact sat-based toffoli network synthesis. ACM Great Lakes Symposium on VLSI Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
2007	—	`conf`	Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
2007	—	`conf`	Formal Verification on the Word Level using SAT-like Proof Techniques. MBMV Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler
2007	—	`conf`	Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?. ICSOFT (SE) Rolf Drechsler, Andreas Breiter
2007	—	`conf`	Improvements for constraint solving in the systemc verification library. ACM Great Lakes Symposium on VLSI Daniel Große, Rüdiger Ebendt, Rolf Drechsler
2007	—	`conf`	Improving Test Pattern Compactness in SAT-based ATPG. ATS Stephan Eggersglüß, Rolf Drechsler
2007	—	`conf`	Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. ISVLSI Ulrich Kühne, Daniel Große, Rolf Drechsler
2007	C	`conf`	Instance Generation for SAT-based ATPG. DDECS Daniel Tille, Görschwin Fey, Rolf Drechsler
2007	C	`conf`	Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. FDL Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
2007	—	`conf`	Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC. ISMVL André Sülflow, Rolf Drechsler
2007	C	`conf`	On the Construction of Small Fully Testable Circuits with Low Depth. DSD Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
2007	—	`conf`	Preface. COCV Sabine Glesner, Jens Knoop, Rolf Drechsler
2007	—	`ed.`	Proceedings of the Workshop on Compiler Optimization meets Compiler Verification, COCV@ETAPS 2007, Braga, Portugal, March 25, 2007 COCV Sabine Glesner, Jens Knoop, Rolf Drechsler
2007	C	`conf`	Proving Completeness of Properties in Formal Verification of Counting Heads for Railways. DSD Sebastian Kinder, Rolf Drechsler
2007	Misc	`conf`	Reusing Learned Information in SAT-based ATPG. VLSI Design Görschwin Fey, Tim Warode, Rolf Drechsler
2007	C	`conf`	Robust Multi-Objective Optimization in High Dimensional Spaces. EMO André Sülflow, Nicole Drechsler, Rolf Drechsler
2007	C	`conf`	SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler
2007	—	`conf`	SWORD: A SAT like Prover Using Word Level Information. VLSI-SoC (Selected Papers) Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
2007	C	`conf`	SWORD: A SAT like prover using word level information. VLSI-SoC Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
2007	J	`jnl`	Technische Dokumentation von Soft- und Hardware in Eingebetteten Systemen (Technical Documentation of Soft- and Hardware in Embedded Systems). it Inf. Technol. Beate Muranko, Rolf Drechsler
2007	—	`conf`	Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse. MBMV André Sülflow, Görschwin Fey, Rolf Drechsler
2007	C	`conf`	Visualization of SystemC Designs. ISCAS Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard
2006	Misc	`conf`	A Framework for Quasi-exact Optimization Using Relaxed Best-First Search. KI Rüdiger Ebendt, Rolf Drechsler
2006	Misc	`conf`	An Integrated Approach for Combining BDD and SAT Provers. VLSI Design Rolf Drechsler, Görschwin Fey, Sebastian Kinder
2006	—	`ed.`	Applications of Evolutionary Computing, EvoWorkshops 2006: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, and EvoSTOC, Budapest, Hungary, April 10-12, 2006, Proceedings EvoWorkshops Franz Rothlauf, Jürgen Branke, Stefano Cagnoni, Ernesto Costa, Carlos Cotta, Rolf Drechsler, Evelyne Lutton, Penousal Machado, Jason H. Moore, Juan Romero, George D. Smith, Giovanni Squillero, Hideyuki Takagi
2006	—	`conf`	Automatic Fault Localization for Property Checking. Haifa Verification Conference Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler
2006	—	`conf`	Automatic Test Pattern Generation. SFM Rolf Drechsler, Görschwin Fey
2006	A	`conf`	Avoiding false negatives in formal verification for protocol-driven blocks. DATE Görschwin Fey, Daniel Große, Rolf Drechsler
2006	J	`jnl`	Effect of improved lower bounds in dynamic BDD reordering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rüdiger Ebendt, Rolf Drechsler
2006	—	`conf`	Efficiency of Multi-Valued Encoding in SAT-based ATPG. ISMVL Görschwin Fey, Junhao Shi, Rolf Drechsler
2006	—	`conf`	Efficient Evolutionary Approaches for the Data Ordering Problem with Inversion. EvoWorkshops Doina Logofatu, Rolf Drechsler
2006	A	`conf`	Efficient minimization of fully testable 2-SPP networks. DATE Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa
2006	—	`conf`	HW/SW co-verification of embedded systems using bounded model checking. ACM Great Lakes Symposium on VLSI Daniel Große, Ulrich Kühne, Rolf Drechsler
2006	C	`conf`	Integrating observability don't cares in all-solution SAT solvers. ISCAS Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
2006	J	`jnl`	Minimizing the number of paths in BDDs: Theory and algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Görschwin Fey, Rolf Drechsler
2006	A	`conf`	On the relation between simulation-based and SAT-based diagnosis. DATE Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
2006	C	`conf`	On the sensitivity of BDDs with respect to path-related objective functions. ISCAS Rüdiger Ebendt, Rolf Drechsler
2006	—	`conf`	SAT-based Calculation of Source Code Coverage for BMC. MBMV Görschwin Fey, Rolf Drechsler
2006	—	`conf`	System Exploration of SystemC Designs. ISVLSI Christian Genz, Rolf Drechsler
2006	C	`conf`	Technical Documentation of Software and Hardware in Embedded Systems. VLSI-SoC Beate Muranko, Rolf Drechsler
2006	—	`conf`	Technische Dokumentation von Soft- und Hardware-Systemen: Die vergessene Welt. MBMV Beate Muranko, Rolf Drechsler
2006	J	`jnl`	Testability of SPP Three-Level Logic Networks in Static Fault Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
2005	—	`conf`	Acceleration of SAT-Based Iterative Property Checking. CHARME Daniel Große, Rolf Drechsler
2005	—	`book`	Advanced BDD optimization. Rüdiger Ebendt, Görschwin Fey, Rolf Drechsler
2005	—	`ed.`	Applications of Evolutionary Computing, EvoWorkshops 2005: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Lausanne, Switzerland, March 30 - April 1, 2005, Proceedings EvoWorkshops Franz Rothlauf, Jürgen Branke, Stefano Cagnoni, David W. Corne, Rolf Drechsler, Yaochu Jin, Penousal Machado, Elena Marchiori, Juan Romero, George D. Smith, Giovanni Squillero
2005	—	`conf`	Bridging fault testability of BDD circuits. ASP-DAC Junhao Shi, Görschwin Fey, Rolf Drechsler
2005	—	`conf`	CheckSyC: an efficient property checker for RTL SystemC designs. ISCAS (4) Daniel Große, Rolf Drechsler
2005	J	`jnl`	Combining ordered best-first search with branch and bound for exact BDD minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
2005	—	`conf`	Controlling the Memory During Manipulation of Word-Level Decision Diagrams. ISMVL Sebastian Kinder, Görschwin Fey, Rolf Drechsler
2005	C	`conf`	Exact BDD Minimization for Path-Related Objective Functions. VLSI-SoC Rüdiger Ebendt, Rolf Drechsler
2005	—	`conf`	Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. GI Jahrestagung (1) Daniel Große, Ulrich Kühne, Rolf Drechsler
2005	J	`jnl`	Generic Implementation of Multi-Valued Logic Decision Diagram Packages. J. Multiple Valued Log. Soft Comput. Rolf Drechsler, Dragan Jankovic, Radomir S. Stankovic
2005	—	`conf`	HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. MTV Daniel Große, Ulrich Kühne, Rolf Drechsler
2005	—	`conf`	Lower bounds for dynamic BDD reordering. ASP-DAC Rüdiger Ebendt, Rolf Drechsler
2005	—	`conf`	PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. ISVLSI Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
2005	—	`conf`	Post-Verification Debugging of Hierarchical Designs. MTV Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
2005	A	`conf`	Post-verification debugging of hierarchical designs. ICCAD Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
2005	—	`conf`	Quasi-Exact BDD Minimization Using Relaxed Best-First Search. ISVLSI Rüdiger Ebendt, Rolf Drechsler
2005	C	`conf`	SyCE: An Integrated Environment for System Design in SystemC. IEEE International Workshop on Rapid System Prototyping Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große
2005	—	`book`	Technische Informatik - eine Einführung. Bernd Becker, Rolf Drechsler, Paul Molitor
2005	—	`conf`	Utilizing don't care states in SAT-based bounded sequential problems. ACM Great Lakes Symposium on VLSI Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler
2004	—	`conf`	A Tight Lower Bound for Dynamic BDD Reordering. MBMV Rüdiger Ebendt, Rolf Drechsler
2004	—	`conf`	Algorithms for Taylor Expansion Diagrams. ISMVL Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski
2004	—	`ed.`	Applications of Evolutionary Computing, EvoWorkshops 2004: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Coimbra, Portugal, April 5-7, 2004, Proceedings EvoWorkshops Günther R. Raidl, Stefano Cagnoni, Jürgen Branke, David Corne, Rolf Drechsler, Yaochu Jin, Colin G. Johnson, Penousal Machado, Elena Marchiori, Franz Rothlauf, George D. Smith, Giovanni Squillero
2004	C	`conf`	BDD Circuit Optimization for Path Delay Fault Testability. DSD Görschwin Fey, Junhao Shi, Rolf Drechsler
2004	C	`conf`	Checkers for SystemC designs. MEMOCODE Daniel Große, Rolf Drechsler
2004	—	`conf`	Combining ordered best-first search with branch and bound for exact BDD minimization. ASP-DAC Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
2004	—	`conf`	Debugging Sequential Circuits Using Boolean Satisfiability. MTV Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith
2004	A	`conf`	Debugging sequential circuits using Boolean satisfiability. ICCAD Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir
2004	—	`conf`	Disjoint Sum of Product Minimization by Evolutionary Algorithms. EvoWorkshops Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler
2004	—	`conf`	Efficient (Non-)Reachability Analysis of Counterexamples. MBMV Rolf Drechsler, Wolfgang Günther, Burkhard Stubert
2004	—	`conf`	Improving simulation-based verification by means of formal methods. ASP-DAC Görschwin Fey, Rolf Drechsler
2004	A	`conf`	Managing Don't Cares in Boolean Satisfiability. DATE Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee
2004	J	`jnl`	Method for Construction of Recursive Algorithms for Reed- Muller-Fourier Polarity Matrices Calculation. J. Multiple Valued Log. Soft Comput. Dragan Jankovic, Rolf Drechsler
2004	—	`conf`	Minimization of the expected path length in BDDs based on local changes. ASP-DAC Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
2004	—	`conf`	Placement and routing optimization for circuits derived from BDDs. ISCAS (5) Thomas Eschbach, Rolf Drechsler, Bernd Becker
2004	—	`conf`	Reduction of Sizes of Multi-Valued Decision Diagrams by Copy Propertie. ISMVL Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler
2004	J	`jnl`	Synthesis of fully testable circuits from BDDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rolf Drechsler, Junhao Shi, Görschwin Fey
2004	C	`conf`	Towards Formal Verification on the System Level. IEEE International Workshop on Rapid System Prototyping Rolf Drechsler
2004	—	`conf`	Using Synthesis Techniques in SAT Solvers. MBMV Rolf Drechsler
2003	J	`jnl`	An improved branch and bound algorithm for exact BDD minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
2003	—	`conf`	Augmented Sifting of Multiple-Valued Decision Diagrams. ISMVL D. Michael Miller, Rolf Drechsler
2003	—	`conf`	BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. Asian Test Symposium Junhao Shi, Görschwin Fey, Rolf Drechsler
2003	—	`conf`	BDD-based verification of scalable designs. HLDVT Daniel Große, Rolf Drechsler
2003	A	`conf`	Combination of Lower Bounds in Exact BDD Minimization. DATE Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
2003	C	`conf`	Efficient Automatic Visualization of SystemC Designs. FDL Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst
2003	J	`jnl`	Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams. IEEE Trans. Computers Wolfgang Günther, Rolf Drechsler
2003	—	`conf`	Efficient Minimization of Multiple-valued Decision Diagrams for Incompletely Specified Functions. ISMVL Denis V. Popel, Rolf Drechsler
2003	J	`jnl`	Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC. it Inf. Technol. Daniel Große, Rolf Drechsler
2003	J	`jnl`	Exact Routing with Search Space Reduction. IEEE Trans. Computers Frank Schmiedle, Rolf Drechsler, Bernd Becker
2003	C	`conf`	Exploration of Sequential Depth by Evolutionary Algorithms. VLSI-SOC Nicole Drechsler, Rolf Drechsler
2003	—	`conf`	Exploration of Sequential Depth by Evolutionary Algorithms. VLSI-SoC (Selected Papers) Nicole Drechsler, Rolf Drechsler
2003	C	`conf`	Fast Heuristics for the Edge Coloring of Large Graphs. DSD Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler
2003	C	`conf`	Finding Good Counter-Examples to Aid Design Verification. MEMOCODE Görschwin Fey, Rolf Drechsler
2003	—	`conf`	Formal verification of LTL formulas for SystemC designs. ISCAS (5) Daniel Große, Rolf Drechsler
2003	—	`conf`	Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen. MBMV Daniel Große, Rolf Drechsler
2003	—	`conf`	GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages. EvoWorkshops Rolf Drechsler, Nicole Drechsler
2003	—	`ed.`	Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25, 2003 MBMV Rolf Drechsler
2003	—	`conf`	Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms. Applied Informatics Rolf Drechsler, Nicole Drechsler
2003	B	`conf`	Minimizing the number of one-paths in BDDs by an evolutionary algorithm. IEEE Congress on Evolutionary Computation Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler
2003	—	`conf`	Modeling Multi-Valued Circuits in SystemC. ISMVL Daniel Große, Görschwin Fey, Rolf Drechsler
2003	—	`conf`	MuTaTe: an efficient design for testability technique for multiplexor based circuits. ACM Great Lakes Symposium on VLSI Rolf Drechsler, Junhao Shi, Görschwin Fey
2003	J	`jnl`	Polynomial Formal Verification of Multipliers. Formal Methods Syst. Des. Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor
2003	J	`jnl`	Recursive bi-partitioning of netlists for large number of partitions. J. Syst. Archit. Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
2003	—	`conf`	Stuck-At-Fault Testability of SPP Three-Level Logic Forms. VLSI-SoC (Selected Papers) Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
2003	—	`conf`	Synthesizing checkers for on-line verification of System-on-Chip designs. ISCAS (4) Rolf Drechsler
2003	C	`conf`	Testability of SPP Three-Level Logic Networks. VLSI-SOC Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
2003	—	`conf`	Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques. ISMVL Görschwin Fey, Sebastian Kinder, Rolf Drechsler
2002	J	`jnl`	A Genetic Algorithm for the Minimization of OPKFDDs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Migyoung Jung, Gueesang Lee, Sungju Park, Rolf Drechsler
2002	—	`conf`	Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. ACM Great Lakes Symposium on VLSI Whitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller
2002	A	`conf`	Crossing Reduction by Windows Optimization. GD Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker
2002	C	`conf`	Decision Diagram Optimization Using Copy Properties. DSD Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler
2002	J	`jnl`	Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts. VLSI Design Marek A. Perkowski, Bogdan J. Falkowski, Malgorzata Chrzanowska-Jeske, Rolf Drechsler
2002	—	`conf`	Evaluation of Static Variable Ordering Heuristics for MDD Construction. ISMVL Rolf Drechsler
2002	J	`jnl`	Heuristic Learning Based on Genetic Programming. Genet. Program. Evolvable Mach. Frank Schmiedle, Nicole Drechsler, Daniel Große, Rolf Drechsler
2002	—	`conf`	Implementation and Visualization of a BDD Package in JAVA. MBMV Rolf Drechsler, Jochen Römmler
2002	J	`jnl`	Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs. VLSI Design Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther
2002	—	`conf`	Low Power Optimization Techniques for BDD Mapped Finite State Machines. IWLS Mikael Kerttu, Per Lindgren, Rolf Drechsler, Mitchell A. Thornton
2002	J	`jnl`	Minimization of Word-Level Decision Diagrams. Integr. Rolf Drechsler, Wolfgang Günther, Stefan Höreth
2002	J	`jnl`	Minimization of free BDDs. Integr. Wolfgang Günther, Rolf Drechsler
2002	—	`conf`	Minimizing the Number of Paths in BDDs. SBCCI Görschwin Fey, Rolf Drechsler
2002	—	`conf`	Multi-Output Timed Shannon Circuits. ISVLSI Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller
2002	—	`conf`	On the Construction of Multiple-Valued Decision Diagrams. ISMVL D. Michael Miller, Rolf Drechsler
2002	—	`conf`	On the Relation between SAT and BDDs for Equivalence Checking. ISQED Sherief Reda, Rolf Drechsler, Alex Orailoglu
2002	—	`conf`	RTL-Datapath Verification using Integer Linear Programming. ASP-DAC/VLSI Design Raik Brinkmann, Rolf Drechsler
2002	C	`conf`	Reachability Analysis for Formal Verification of SystemC. DSD Rolf Drechsler, Daniel Große
2002	C	`conf`	Recursive Bi-Partitioning of Netlists for Large Number of Partitions. DSD Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
2002	—	`conf`	Switching activity estimation of finite state machines for low power synthesis. ISCAS (4) Mikael Kerttu, Per Lindgren, Mitchell A. Thornton, Rolf Drechsler
2002	—	`conf`	Symbolic Simulation of Algorithms Specified in HDL. MBMV Klaus-Jürgen Englert, Bernd Becker, Rolf Drechsler
2002	J	`jnl`	Verifying integrity of decision diagrams. Integr. Rolf Drechsler
2001	J	`jnl`	Binary decision diagrams in theory and practice. Int. J. Softw. Tools Technol. Transf. Rolf Drechsler, Detlef Sieling
2001	J	`jnl`	Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. J. Electron. Test. Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
2001	J	`jnl`	Decision Diagram Method for Calculation of Pruned Walsh Transform. IEEE Trans. Computers Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler
2001	—	`conf`	GateComp: Equivalence Checking in CVE. MBMV (1) Rolf Drechsler
2001	C	`conf`	Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. DSD Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Günther
2001	B	`conf`	Heuristic Learning Based on Genetic Programming. EuroGP Nicole Drechsler, Frank Schmiedle, Daniel Große, Rolf Drechsler
2001	J	`jnl`	History-based dynamic BDD minimization. Integr. Rolf Drechsler, Wolfgang Günther
2001	Misc	`conf`	Implementation of Read- k-times BDDs on Top of Standard BDD Packages. VLSI Design Wolfgang Günther, Rolf Drechsler
2001	C	`conf`	Level Assignment for Displaying Combinational Logic. DSD Rolf Drechsler, Wolfgang Günther, Lothar Linhard, Gerhard Angst
2001	—	`conf`	Low power optimization technique for BDD mapped circuits. ASP-DAC Per Lindgren, Mikael Kerttu, Mitchell A. Thornton, Rolf Drechsler
2001	C	`conf`	Minimization of OPKFDDs Using Genetic Algorithms. DSD Migyoung Jung, Gueesang Lee, Sungju Park, Rolf Drechsler
2001	C	`conf`	Multi-objective Optimisation Based on Relation EMO Nicole Drechsler, Rolf Drechsler, Bernd Becker
2001	Misc	`conf`	Performance Driven Optimization for MUX based FPGAs. VLSI Design Wolfgang Günther, Rolf Drechsler
2001	—	`conf`	Selection of Efficient Re-Ordering Heuristics for MDD Construction. ISMVL Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
2001	A	`conf`	Spectral decision diagrams using graph transformations. DATE Mitchell A. Thornton, Rolf Drechsler
2001	—	`book`	Spectral techniques in VLSI CAD. Mitchell Aaron Thornton, Rolf Drechsler, D. Michael Miller
2001	C	`conf`	Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths. VLSI-SOC Peer Johannsen, Rolf Drechsler
2001	—	`conf`	Tabular Techniques for MV Logic. ACS Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler
2001	—	`conf`	Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics. Fuzzy Days Frank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker
2001	J	`jnl`	Using lower bounds during dynamic BDD minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rolf Drechsler, Wolfgang Günther, Fabio Somenzi
2001	—	`conf`	Utilizing High-Level Information for Formal Hardware Verification. ACS Peer Johannsen, Rolf Drechsler
2001	J	`jnl`	Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld (Equivalence Checking of Digital Circuits in an Industrial Environment). Informationstechnik Tech. Inform. Rolf Drechsler
2000	—	`conf`	A Method for Approximate Equivalence Checking. ISMVL Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther
2000	—	`conf`	ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs. EUROMICRO Wolfgang Günther, Rolf Drechsler
2000	J	`jnl`	ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs. J. Syst. Archit. Wolfgang Günther, Rolf Drechsler
2000	J	`jnl`	Boolean function representation and spectral characterization using AND/OR graphs. Integr. A. Zuzek, Rolf Drechsler, Mitchell A. Thornton
2000	—	`conf`	Computation of Spectral Information from Logic Netlists. ISMVL Rolf Drechsler, Mitchell A. Thornton
2000	—	`conf`	Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System. EUROMICRO Rolf Drechsler, Nicole Drechsler, Elke Mackensen, Tobias Schubert, Bernd Becker
2000	—	`conf`	Dynamic Re-Encoding During MDD Minimization. ISMVL Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
2000	C	`conf`	Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation. ICCD Wolfgang Günther, Rolf Drechsler, Stefan Höreth
2000	A	`conf`	Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints. GECCO Rolf Drechsler, Wolfgang Günther
2000	J	`jnl`	Fast exact minimization of BDD's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
2000	A	`conf`	Improving EAs for Sequencing Problems. GECCO Wolfgang Günther, Rolf Drechsler
2000	—	`conf`	Lower Bound Sifting for MDDs. ISMVL Dragan Jankovic, Wolfgang Günther, Rolf Drechsler
2000	—	`conf`	MDD-Based Synthesis of Multi-Valued Logic Networks. ISMVL Rolf Drechsler, Mitchell A. Thornton, David Wessels
2000	C	`conf`	Minimization of Ordered Pseudo Kronecker Decision Diagrams. ICCD Per Lindgren, Rolf Drechsler, Bernd Becker
2000	J	`jnl`	OKFDD minimization by genetic algorithms with application to circuit design. Integr. Rolf Drechsler, Bernd Becker, Nicole Drechsler
2000	J	`jnl`	On the computational power of linearly transformed BDDs. Inf. Process. Lett. Wolfgang Günther, Rolf Drechsler
2000	C	`conf`	Optimization of sequential verification by history-based dynamic minimization of BDDs. ISCAS Rolf Drechsler, Wolfgang Günther
2000	A	`conf`	Specialized Hardware for Implementation of Evolutionary Algorithms. GECCO Tobias Schubert, Elke Mackensen, Nicole Drechsler, Rolf Drechsler, Bernd Becker
2000	—	`conf`	Testability of Circuits Derived from Lattice Diagrams. EUROMICRO Rolf Drechsler, Wolfgang Günther, Bernd Becker
2000	—	`conf`	Testability of Circuits Derived from Lattice Diagrams. LATW Rolf Drechsler, Wolfgang Günther, Bernd Becker
2000	—	`conf`	Verification of Designs Containing Black Boxes. EUROMICRO Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
2000	—	`conf`	Verification of Designs Containing Black Boxes. MBMV Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
1999	J	`jnl`	BDD minimization using symmetries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler
1999	—	`conf`	Checking Integrity During Dynamic Reordering in Decision Diagrams. EUROMICRO Rolf Drechsler
1999	—	`conf`	Creating hard problem instances in logic synthesis using exact minimization. ISCAS (6) Wolfgang Günther, Rolf Drechsler
1999	—	`conf`	Design of experiments in CAD: context and new data sets for ISCAS'99. ISCAS (6) Franc Brglez, Rolf Drechsler
1999	—	`conf`	Efficient Graph Coloring by Evolutionary Algorithms. Fuzzy Days Nicole Drechsler, Wolfgang Günther, Rolf Drechsler
1999	A	`conf`	Efficient manipulation algorithms for linearly transformed BDDs. ICCAD Wolfgang Günther, Rolf Drechsler
1999	J	`jnl`	Evolutionary Algorithms for VLSI CAD [book Review]. IEEE Trans. Evol. Comput. Rolf Drechsler
1999	—	`conf`	Exact channel routing using symbolic representation. ISCAS (6) Frank Schmiedle, Rolf Drechsler, Bernd Becker
1999	—	`conf`	Exploiting Don't Caers During Data Sequencing using Genetic Algorithms. ASP-DAC Rolf Drechsler, Nicole Drechsler
1999	A	`conf`	Formal Verification of Word-Level Specifications. DATE Stefan Höreth, Rolf Drechsler
1999	—	`conf`	Generation of Optimal Universal Logic Modules. EUROMICRO Rolf Drechsler, Wolfgang Günther
1999	—	`conf`	Generic Implementation of DD Packages in MVL. EUROMICRO Rolf Drechsler, Dragan Jankovic, Radomir S. Stankovic
1999	—	`conf`	Grouping Heuristics for Word-Level Decision Diagrams. MBMV Rolf Drechsler, Marc Herbstritt, Bernd Becker
1999	—	`conf`	Grouping heuristics for word-level decision diagrams. ISCAS (1) Rolf Drechsler, Marc Herbstritt, Bernd Becker
1999	—	`conf`	History-Based Dynamic Minimization During BDD Construction. VLSI Rolf Drechsler, Wolfgang Günther
1999	—	`conf`	Minimization of BDDs using linear transformations based on evolutionary techniques. ISCAS (1) Wolfgang Günther, Rolf Drechsler
1999	—	`conf`	Minimization of Free BDDs. ASP-DAC Wolfgang Günther, Rolf Drechsler
1999	—	`conf`	Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes. Fuzzy Days Nicole Drechsler, Rolf Drechsler, Bernd Becker
1999	—	`conf`	Power Consumption in XOR-Based Circuits. ASP-DAC Yibin Ye, Kaushik Roy, Rolf Drechsler
1999	J	`jnl`	Preudo-Kronecker Expressions for Symmetric Functions. IEEE Trans. Computers Rolf Drechsler
1999	C	`conf`	Synthesis of Pseudo Kronecker Lattice Diagrams. ICCD Per Lindgren, Rolf Drechsler, Bernd Becker
1999	J	`jnl`	Testability of 2-Level AND/EXOR Circuits. J. Electron. Test. Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker
1999	A*	`conf`	Using Lower Bounds During Dynamic BDD Minimization. DAC Rolf Drechsler, Wolfgang Günther
1999	A	`conf`	Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities. DATE Mitchell A. Thornton, J. P. Williams, Rolf Drechsler, Nicole Drechsler
1998	—	`book`	Binary Decision Diagrams - Theory and Implementation. Rolf Drechsler, Bernd Becker
1998	A	`conf`	Dynamic Minimization of Word-Level Decision Diagrams. DATE Stefan Höreth, Rolf Drechsler
1998	—	`conf`	ETDD-Based Synthesis of Term-Based FPGAs for Incompletely Specified Boolean Functions. ASP-DAC Gueesang Lee, Rolf Drechsler
1998	A*	`conf`	Fast Exact Minimization of BDDs. DAC Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
1998	—	`book`	Graphenbasierte Funktionsdarstellung - Boolesche und Pseudo-Boolesche Funktionen. Rolf Drechsler, Bernd Becker
1998	—	`conf`	Implementing a Multiple-Valued Decision Diagram Package. ISMVL D. Michael Miller, Rolf Drechsler
1998	—	`conf`	Linear Transformations and Exact Minimization of BDDs. Great Lakes Symposium on VLSI Wolfgang Günther, Rolf Drechsler
1998	—	`conf`	Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions. ISMVL Per Lindgren, Rolf Drechsler, Bernd Becker
1998	—	`conf`	Manipulation of *BMDs. ASP-DAC Rolf Drechsler, Stefan Höreth
1998	J	`jnl`	On Variable Ordering and Decomposition Type Choice in OKFDDs. IEEE Trans. Computers Rolf Drechsler, Bernd Becker, Andrea Jahnke
1998	J	`jnl`	Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rolf Drechsler, Bernd Becker
1998	—	`conf`	Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm. ISMVL Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
1998	J	`jnl`	The complexity of the inclusion operation on OFDD's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rolf Drechsler, Martin Sauerhoff, Detlef Sieling
1998	B	`conf`	Verifying Integrity of Decision Diagrams. SAFECOMP Rolf Drechsler
1997	Misc	`conf`	(Quasi-) Linear Path Delay Fault Tests for Adders. VLSI Design Bernd Becker, Rolf Drechsler, Sudhakar M. Reddy
1997	C	`conf`	A multi-layer detailed routing approach based on evolutionary algorithms. ICEC Nicole Göckel, Rolf Drechsler, B. Becker
1997	—	`conf`	Circuit Design from Kronecker Galois Field Decision Diagrams for Multiple-Valued Functions. ISMVL Radomir S. Stankovic, Rolf Drechsler
1997	Misc	`conf`	Decision Diagrams in Synthesis - Algorithms, Applications and Extensions. VLSI Design Bernd Becker, Rolf Drechsler
1997	—	`conf`	Fast and efficient construction of BDDs by reordering based synthesis. ED&TC Andreas Hett, Rolf Drechsler, Bernd Becker
1997	—	`conf`	Fault Simulation in Sequential Multi-Valued Logic Networks. ISMVL Rolf Drechsler, Martin Keim, Bernd Becker
1997	—	`conf`	Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams. ISMVL Craig M. Files, Rolf Drechsler, Marek A. Perkowski
1997	A	`conf`	Functional simulation using binary decision diagrams. ICCAD Christoph Scholl, Rolf Drechsler, Bernd Becker
1997	C	`conf`	Influencing parameters of evolutionary algorithms for sequencing problems. ICEC Nicole Göckel, Rolf Drechsler
1997	—	`conf`	Learning heuristics for OKFDD minimization by evolutionary algorithms. ASP-DAC Nicole Göckel, Rolf Drechsler, Bernd Becker
1997	A	`conf`	Manipulation Algorithms for K*BMDs. TACAS Rolf Drechsler, Bernd Becker, Stefan Ruppertz
1997	J	`jnl`	On the Expressive Power of OKFDDs. Formal Methods Syst. Des. Bernd Becker, Rolf Drechsler, Michael Theobald
1997	—	`conf`	On the representational power of bit-level and word-level decision diagrams. ASP-DAC Bernd Becker, Rolf Drechsler, Reinhard Enders
1997	Misc	`conf`	Polynomial Formal Verification of Multipliers. VTS Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor
1997	Misc	`conf`	Pseudo Kronecker Expressions for Symmetric Functions. VLSI Design Rolf Drechsler
1997	—	`conf`	Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions. ISMVL Rolf Drechsler, Martin Keim, Bernd Becker
1997	J	`jnl`	Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rolf Drechsler, Bernd Becker
1997	—	`conf`	Testability of 2-level AND/EXOR circuits. ED&TC Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker
1997	J	`jnl`	The K*BMD: A Verification Data Structure. IEEE Des. Test Comput. Rolf Drechsler, Bernd Becker, Stefan Ruppertz
1996	—	`conf`	A Fast Optimal Robust Path Delay Fault Testable Adder. ED&TC Bernd Becker, Rolf Drechsler, Rolf Krieger, Sudhakar M. Reddy
1996	—	`conf`	AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth. Asian Test Symposium Harry Hengster, Rolf Drechsler, Bernd Becker, Stefan Eckrich, Tonja Pfeiffer
1996	J	`jnl`	Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions. IEEE Trans. Computers Rolf Drechsler, Michael Theobald, Bernd Becker
1996	—	`conf`	K*BMDs: A New Data Structure for Verification. ED&TC Rolf Drechsler, Bernd Becker, Stefan Ruppertz
1996	A	`conf`	Learning Heuristics for OBDD Minimization by Evolutionary Algorithms. PPSN Rolf Drechsler, Nicole Göckel, Bernd Becker
1996	—	`conf`	MORE: an alternative implementation of BDD packages by multi-operand synthesis. EURO-DAC Andreas Hett, Bernd Becker, Rolf Drechsler
1996	—	`—`	Ordered Kronecker functional decision diagrams und ihre Anwendung. Rolf Drechsler
1996	—	`conf`	Verification of Multi-Valued Logic Networks. ISMVL Rolf Drechsler
1995	J	`jnl`	A Genetic Algorithm for Decomposition Type Choice in OKFDDs. Int. J. Artif. Intell. Tools Rolf Drechsler, Bernd Becker, Nicole Göckel, Andrea Jahnke
1995	—	`conf`	A Genetic Algorithm for Minimization of Fixed Polarity Reed-Muller Expressions. ICANNGA Rolf Drechsler, Bernd Becker, Nicole Göckel
1995	C	`conf`	Dynamic minimization of OKFDDs. ICCD Rolf Drechsler, Bernd Becker
1995	—	`conf`	How many decomposition types do we need? [decision diagrams]. ED&TC Bernd Becker, Rolf Drechsler
1995	—	`conf`	Learning heuristics by genetic algorithms. ASP-DAC Rolf Drechsler, Bernd Becker
1995	A*	`conf`	OKFDDs versus OBDDs and OFDDs. ICALP Bernd Becker, Rolf Drechsler, Michael Theobald
1995	J	`jnl`	On local transformations and path delay fault testability. J. Electron. Test. Harry Hengster, Rolf Drechsler, Bernd Becker
1995	B	`conf`	On the Relation Betwen BDDs and FDDs. LATIN Bernd Becker, Rolf Drechsler, Ralph Werchner
1995	J	`jnl`	On the Relation between BDDs and FDDs. Inf. Comput. Bernd Becker, Rolf Drechsler, Ralph Werchner
1995	Misc	`conf`	On the application of local circuit transformations with special emphasis on path delay fault testability. VTS Harry Hengster, Rolf Drechsler, Bernd Becker
1995	J	`jnl`	On the generation of area-time optimal testable adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bernd Becker, Rolf Drechsler, Paul Molitor
1995	—	`conf`	Random Pattern Fault Simulation in Multi-Valued Circuits. ISMVL Rolf Drechsler, Rolf Krieger, Bernd Becker
1995	—	`conf`	Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions. ED&TC Rolf Drechsler, Bernd Becker
1995	—	`conf`	Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams. ED&TC Bernd Becker, Rolf Drechsler
1994	—	`conf`	BiTeS: a BDD based test pattern generator for strong robust path delay faults. EURO-DAC Rolf Drechsler
1994	—	`conf`	Efficient Graph Based Representation of Multi-Valued Functions with an Application to Genetic Algorithms. ISMVL Bernd Becker, Rolf Drechsler
1994	A*	`conf`	Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams. DAC Rolf Drechsler, Andisheh Sarabi, Michael Theobald, Bernd Becker, Marek A. Perkowski
1994	—	`conf`	Fast OFDD based minimization of fixed polarity Reed-Muller expressions. EURO-DAC Rolf Drechsler, Bernd Becker, Michael Theobald
1994	C	`conf`	OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms. ICCD Bernd Becker, Rolf Drechsler
1994	Misc	`conf`	Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model. VLSI Design Harry Hengster, Rolf Drechsler, Bernd Becker
1994	—	`conf`	Testability of Circuits Derived from Functional Decision Diagrams. EDAC-ETC-EUROASIC Bernd Becker, Rolf Drechsler
1993	—	`conf`	On the implementation of an efficient performance driven generator for conditional-sum-adders. EURO-DAC Bernd Becker, Rolf Drechsler, Paul Molitor
1992	—	`conf`	A time optimal robust path-delay-fault self-testable adder. EURO-DAC Bernd Becker, Rolf Drechsler