Roland Dobai

20 papers B 2C 5Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2019 J jnl
Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques.
IEEE Trans. Very Large Scale Integr. Syst.
Vojtech Mrazek, Lukás Sekanina, Roland Dobai, Marek Sýs, Petr Svenda
2017 — conf
Designing bent boolean functions with parallelized linear genetic programming.
GECCO (Companion)
Jakub Husa, Roland Dobai
2017 J jnl
Evolutionary design of hash function pairs for network filters.
Appl. Soft Comput.
Roland Dobai, Jan Korenek, Lukás Sekanina
2017 B conf
Evolutionary design of hash functions for IP address hashing using genetic programming.
CEC
Marek Kidon, Roland Dobai
2016 — conf
Adaptive development of hash functions in FPGA-based network routers.
SSCI
Roland Dobai, Jan Korenek, Lukás Sekanina
2015 — conf
Evolution of Non-Cryptographic Hash Function Pairs for FPGA-Based Network Applications.
SSCI
Roland Dobai, Jan Korenek
2015 J jnl
Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware.
ACM Trans. Reconfigurable Technol. Syst.
Roland Dobai, Lukás Sekanina
2014 — conf
Evolutionary digital circuit design with fast candidate solution establishment in field programmable gate arrays.
ICES
Roland Dobai, Kyrre Glette, Jim Tørresen, Lukás Sekanina
2014 B conf
Evolutionary on-line synthesis of hardware accelerators for software modules in reconfigurable embedded systems.
FPL
Roland Dobai
2013 J jnl
Compressed Skewed-Load Delay Test Generation Based on Evolution and Deterministic Initialization of Populations.
Comput. Informatics
Roland Dobai, Marcel Baláz
2013 — conf
Image filter evolution on the Xilinx Zynq Platform.
AHS
Roland Dobai, Lukás Sekanina
2013 J jnl
SAT-based generation of compressed skewed-load tests for transition delay faults.
Microprocess. Microsystems
Roland Dobai, Marcel Baláz
2013 — conf
Towards evolvable systems based on the Xilinx Zynq platform.
ICES
Roland Dobai, Lukás Sekanina
2012 C conf
Automated Generation of Built-In Self-Repair Architectures for Random Logic SoC Cores.
DSD
Roland Dobai, Marcel Baláz, Mária Fischerová
2012 C conf
Genetic method for compressed skewed-load delay test generation.
DDECS
Roland Dobai, Marcel Baláz
2011 J jnl
A novel automatic test pattern generator for asynchronous sequential digital circuits.
Microelectron. J.
Roland Dobai, Elena Gramatová
2011 C conf
SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults.
DSD
Roland Dobai, Marcel Baláz
2010 J jnl
Deductive Fault Simulation Technique for Asynchronous Circuits.
Comput. Informatics
Roland Dobai, Elena Gramatová
2010 C conf
Test pattern generation for the combinational representation of asynchronous circuits.
DDECS
Roland Dobai, Elena Gramatová
2009 C conf
Deductive Fault Simulation for Asynchronous Sequential Circuits.
DSD
Roland Dobai, Elena Gramatová