Roger F. Woods

169 papers A 3B 15C 3Misc 21Journal 66Unranked 55

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Efficient Implementation of AI Algorithms on an FPGA-Based System for Enhancing Blood Vessel Segmentation. Int. J. Parallel Program. Majed Alsharari, Son T. Mai, Romain Garnier, Carlos Reaño, Roger F. Woods
2025	J	`jnl`	A Novel Error Metric for Evaluating the Error Correction Capability of Approximate Units. IEEE Trans. Circuits Syst. II Express Briefs Yuqin Dou, Zhikuang Cai, Haroon Waris, Roger F. Woods, Weiqiang Liu
2025	J	`jnl`	Efficient Integer-Only-Inference of Gradient Boosting Decision Trees on Low-Power Devices. IEEE Trans. Circuits Syst. I Regul. Pap. Majed Alsharari, Son T. Mai, Roger F. Woods, Carlos Reaño
2025	—	`conf`	Enhancing the Real-Time Solutions of Parametric Linear Systems on a GPU through Hybrid Coarse-Grained Transprecision Computing. HPEC Hamid Noori, Hans Vandierendonck, Roger F. Woods, Nick Polydorides
2025	—	`conf`	Predictive Quality of In-Fabrication Products in Smart Manufacturing Using Graph-Based Deep Learning. ICINCO (1) Peter Davison, Muhammad Fahim, Roger F. Woods, Scott Fischaber, Marcus Haron, Cormac McAteer
2025	—	`conf`	Randomised sketching of parametric linear systems. SSP Nick Polydorides, Hamid Noori, Hans Vandierendonck, Roger F. Woods
2024	J	`jnl`	A Systematic Approach to Filter Specification for Measuring Quasi-Static Bridge Rotation Under Moving Loads Using DC Accelerometers. IEEE Access Alan J. Ferguson, David Hester, Roger F. Woods
2024	J	`jnl`	Adaptive approximate computing in edge AI and IoT applications: A review. J. Syst. Archit. Hans Jakob Damsgaard, Antoine Grenier, Dewant Katare, Zain Taufique, Salar Shakibhamedan, Tiago Troccoli, Georgios Chatzitsompanis, Anil Kanduri, Aleksandr Ometov, Aaron Yi Ding, Nima Taherinejad, Georgios Karakonstantis, Roger F. Woods, Jari Nurmi
2024	J	`jnl`	CACTUS: A Comprehensive Abstraction and Classification Tool for Uncovering Structures. ACM Trans. Intell. Syst. Technol. Luca Gherardini, Varun Ravi Varma, Karol Capala, Roger F. Woods, José L. R. Sousa
2024	J	`jnl`	FPAX: A Fast Prior Knowledge-Based Framework for DSE in Approximate Configurations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuqin Dou, Chenghua Wang, Haroon Waris, Roger F. Woods, Weiqiang Liu
2024	J	`jnl`	Towards Receiver-Agnostic and Collaborative Radio Frequency Fingerprint Identification. IEEE Trans. Mob. Comput. Guanxiong Shen, Junqing Zhang, Alan Marshall, Roger F. Woods, Joseph R. Cavallaro, Liquan Chen
2023	—	`conf`	An Intelligent Image Processing System for Enhancing Blood Vessel Segmentation on Low-Power SoC. SAMOS Majed Alsharari, Son T. Mai, Romain Garnier, Carlos Reaño, Roger F. Woods
2023	J	`jnl`	CACTUS: a Comprehensive Abstraction and Classification Tool for Uncovering Structures. CoRR Luca Gherardini, Varun Ravi Varma, Karol Capala, Roger F. Woods, José L. R. Sousa
2023	J	`jnl`	ENAP: An Efficient Number-Aware Pruning Framework for Design Space Exploration of Approximate Configurations. IEEE Trans. Circuits Syst. I Regul. Pap. Yuqin Dou, Chenghua Wang, Roger F. Woods, Weiqiang Liu
2022	J	`jnl`	A Soft Coprocessor Approach for Developing Image and Video Processing Applications on FPGAs. J. Imaging Tiantai Deng, Danny Crookes, Roger F. Woods, Fahad Manzoor Siddiqui
2022	J	`jnl`	Detecting Vehicle Loading Events in Bridge Rotation Data Measured with Multi-Axial Accelerometers. Sensors Alan J. Ferguson, Roger F. Woods, David Hester
2022	J	`jnl`	Efficient, Dynamic Multi-Task Execution on FPGA-Based Computing Systems. IEEE Trans. Parallel Distributed Syst. Umar Ibrahim Minhas, Roger F. Woods, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
2022	J	`jnl`	Increased Leverage of Transprecision Computing for Machine Vision Applications at the Edge. J. Signal Process. Syst. Umar Ibrahim Minhas, JunKyu Lee, Lev Mukhanov, Georgios Karakonstantis, Hans Vandierendonck, Roger F. Woods
2022	—	`conf`	Multi-spectral In-Vivo FPGA-Based Surgical Imaging. ARC Majed Alsharari, Lorenzo Niemitz, Simon Sorensen, Roger F. Woods, Ray Burke, Stefan Andersson-Engels, Carlos Reaño, Son T. Mai
2021	J	`jnl`	Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs. J. Signal Process. Syst. Umar Ibrahim Minhas, Roger F. Woods, Georgios Karakonstantis
2021	—	`conf`	Leveraging Transprecision Computing for Machine Vision Applications at the Edge. SiPS Umar Ibrahim Minhas, Lev Mukhanov, Georgios Karakonstantis, Hans Vandierendonck, Roger F. Woods
2021	J	`jnl`	Leveraging Transprecision Computing for Machine Vision Applications at the Edge. CoRR Umar Ibrahim Minhas, Lev Mukhanov, Georgios Karakonstantis, Hans Vandierendonck, Roger F. Woods
2021	J	`jnl`	Radio Frequency Fingerprint Identification for Narrowband Systems, Modelling and Classification. IEEE Trans. Inf. Forensics Secur. Junqing Zhang, Roger F. Woods, Magnus Sandell, Mikko Valkama, Alan Marshall, Joseph R. Cavallaro
2021	C	`conf`	TOD: Transprecise Object Detection to Maximise Real-Time Accuracy on the Edge. ICFEC JunKyu Lee, Blesson Varghese, Roger F. Woods, Hans Vandierendonck
2021	J	`jnl`	TOD: Transprecise Object Detection to Maximise Real-Time Accuracy on the Edge. CoRR JunKyu Lee, Blesson Varghese, Roger F. Woods, Hans Vandierendonck
2019	J	`jnl`	An Investigation of Using Loop-Back Mechanism for Channel Reciprocity Enhancement in Secret Key Generation. IEEE Trans. Mob. Comput. Linning Peng, Guyue Li, Junqing Zhang, Roger F. Woods, Ming Liu, Aiqun Hu
2019	—	`ed.`	Applied Reconfigurable Computing - 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9-11, 2019, Proceedings ARC Christian Hochberger, Brent Nelson, Andreas Koch, Roger F. Woods, Pedro C. Diniz
2019	Misc	`conf`	Design space exploration of multi-task processing on space shared FPGAs: work-in-progress. CODES+ISSS Umar Ibrahim Minhas, Roger F. Woods, Georgios Karakonstantis
2019	—	`conf`	Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks. ARC Umar Ibrahim Minhas, Roger F. Woods, Georgios Karakonstantis
2019	J	`jnl`	FPGA-Based Processor Acceleration for Image Processing Applications. J. Imaging Fahad Manzoor Siddiqui, Sam Amiri, Umar Ibrahim Minhas, Tiantai Deng, Roger F. Woods, Karen Rafferty, Daniel Crookes
2019	J	`jnl`	Impact of Wireless Backhaul Unreliability and Imperfect Channel Estimation on Opportunistic NOMA. IEEE Trans. Veh. Technol. Sunyoung Lee, Trung Q. Duong, Roger F. Woods
2019	—	`conf`	Optimisation of System Throughput Exploiting Tasks Heterogeneity on Space Shared FPGAs. FPT Umar Ibrahim Minhas, Roger F. Woods, Georgios Karakonstantis
2019	J	`jnl`	Physical Layer Security for the Internet of Things: Authentication and Key Generation. IEEE Wirel. Commun. Junqing Zhang, Sekhar Rajendran, Zhi Sun, Roger F. Woods, Lajos Hanzo
2018	—	`conf`	A Bayesian network based learning system for modelling faults in large-scale manufacturing. ICIT Caoimhe M. Carbery, Roger F. Woods, Adele H. Marshall
2018	—	`conf`	Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through Platform-Independent Optimizations. ARC Umar Ibrahim Minhas, Roger F. Woods, George Karakonstantis
2018	B	`conf`	Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems. FPL Umar Ibrahim Minhas, Roger F. Woods, Georgios Karakonstantis
2018	J	`jnl`	NanoStreams: A Microserver Architecture for Real-Time Analytics on Fast Data Streams. IEEE Trans. Multi Scale Comput. Syst. Umar Ibrahim Minhas, Matthew Russell, Stelios Kaloutsakis, Paul Barber, Roger F. Woods, Giorgis Georgakoudis, Charles Gillan, Dimitrios S. Nikolopoulos, Angelos Bilas
2018	B	`conf`	Opportunistic Non-Orthogonal Multiple Access Scheme with Unreliable Wireless Backhauls. PIMRC Sunyoung Lee, Trung Quang Duong, Roger F. Woods
2018	J	`jnl`	Security Optimization of Exposure Region-Based Beamforming With a Uniform Circular Array. IEEE Trans. Commun. Yuanrui Zhang, Roger F. Woods, Youngwook Ko, Alan Marshall, Junqing Zhang
2017	J	`jnl`	Defining Spatial Secrecy Outage Probability for Exposure Region-Based Beamforming. IEEE Trans. Wirel. Commun. Yuanrui Zhang, Youngwook Ko, Roger F. Woods, Alan Marshall
2017	J	`jnl`	Design of an OFDM Physical Layer Encryption Scheme. IEEE Trans. Veh. Technol. Junqing Zhang, Alan Marshall, Roger F. Woods, Trung Quang Duong
2017	J	`jnl`	FPGA-Based Soft-Core Processors for Image Processing Applications. J. Signal Process. Syst. Moslem Amiri, Fahad Manzoor Siddiqui, Colm Kelly, Roger F. Woods, Karen Rafferty, Burak Bardak
2017	J	`jnl`	On the Key Generation From Correlated Wireless Channels. IEEE Commun. Lett. Junqing Zhang, Biao He, Trung Quang Duong, Roger F. Woods
2017	J	`jnl`	Securing Wireless Communications of the Internet of Things from the Physical Layer, An Overview. CoRR Junqing Zhang, Trung Quang Duong, Roger F. Woods, Alan Marshall
2017	J	`jnl`	Securing Wireless Communications of the Internet of Things from the Physical Layer, An Overview. Entropy Junqing Zhang, Trung Quang Duong, Roger F. Woods, Alan Marshall
2016	J	`jnl`	Defining Spatial Security Outage Probability for Exposure Region Based Beamforming. CoRR Yuanrui Zhang, Youngwook Ko, Roger F. Woods, Alan Marshall
2016	J	`jnl`	Efficient Key Generation by Exploiting Randomness From Channel Responses of Individual OFDM Subcarriers. IEEE Trans. Commun. Junqing Zhang, Alan Marshall, Roger F. Woods, Trung Quang Duong
2016	J	`jnl`	Experimental Study on Key Generation for Physical Layer Security in Wireless Communications. IEEE Access Junqing Zhang, Roger F. Woods, Trung Quang Duong, Alan Marshall, Yuan Ding, Yi Huang, Qian Xu
2016	—	`conf`	Experimental study on channel reciprocity in wireless key generation. SPAWC Junqing Zhang, Roger F. Woods, Trung Quang Duong, Alan Marshall, Yuan Ding
2016	—	`conf`	FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG. ARC Colm Kelly, Fahad Manzoor Siddiqui, Burak Bardak, Yun Wu, Roger F. Woods, Karen Rafferty
2016	J	`jnl`	Key Generation From Wireless Channels: A Review. IEEE Access Junqing Zhang, Trung Quang Duong, Alan Marshall, Roger F. Woods
2016	—	`conf`	NanoStreams: Codesigned microservers for edge analytics in real time. SAMOS Giorgis Georgakoudis, Charles Gillan, Ahmad Hassan, Umar Ibrahim Minhas, Ivor T. A. Spence, George Tzenakis, Hans Vandierendonck, Roger F. Woods, Dimitrios S. Nikolopoulos, Murali Shyamsundar, Paul Barber, Matthew Russell, Angelos Bilas, Stelios Kaloutsakis, Heiner Giefers, Peter W. J. Staar, Costas Bekas, Neil Horlock, Richard Faloon, Colin Pattison
2016	Misc	`conf`	On spatial security outage probability derivation of exposure region based beamforming with randomly located eavesdroppers. ACSSC Yuanrui Zhang, Youngwook Ko, Roger F. Woods, Alan Marshall, Joe Cavallaro, Kaipeng Li
2016	Misc	`conf`	On spatial security outage probability derivation of exposure region based beamforming with randomly located eavesdroppers. ACSSC Yuanrui Zhang, Youngwook Ko, Roger F. Woods, Alan Marshall, Joe Cavallaro, Kaipeng Li
2016	B	`conf`	Proposing the Deep Dynamic Bayesian Network as a Future Computer Based Medical System. CBMS Caoimhe M. Carbery, Adele H. Marshall, Roger F. Woods
2016	—	`conf`	Runtime support for adaptive power capping on heterogeneous SoCs. SAMOS Yun Wu, Dimitrios S. Nikolopoulos, Roger F. Woods
2015	Misc	`conf`	An effective key generation system using improved channel reciprocity. ICASSP Junqing Zhang, Roger F. Woods, Alan Marshall, Trung Quang Duong
2015	—	`conf`	Verification of Key Generation from Individual OFDM Subcarrier's Channel Response. GLOBECOM Workshops Junqing Zhang, Roger F. Woods, Alan Marshall, Trung Quang Duong
2014	B	`conf`	Creating secure wireless regions using configurable beamforming. PIMRC Yuanrui Zhang, Alan Marshall, Roger F. Woods, Youngwook Ko
2014	Misc	`conf`	Dataflow toolset for soft-core processors on FPGA for image processing applications. ACSSC Burak Bardak, Fahad Manzoor Siddiqui, Colm Kelly, Roger F. Woods
2014	—	`conf`	Histogram of oriented gradients front end processing: An FPGA based processor approach. SiPS Colm Kelly, Fahad Manzoor Siddiqui, Burak Bardak, Roger F. Woods
2014	—	`conf`	IPPro: FPGA based image processing processor. SiPS Fahad Manzoor Siddiqui, Matthew Russell, Burak Bardak, Roger F. Woods, Karen Rafferty
2014	Misc	`conf`	Investigation of secure wireless regions using configurable beamforming on WARP. ACSSC Yuanrui Zhang, Bei Yin, Roger F. Woods, Joseph R. Cavallaro, Alan Marshall, Youngwook Ko
2014	—	`conf`	Power modelling and capping for heterogeneous ARM/FPGA SoCs. FPT Yun Wu, José L. Núñez-Yáñez, Roger F. Woods, Dimitrios S. Nikolopoulos
2014	—	`conf`	Secure key generation from OFDM subcarriers' channel responses. GLOBECOM Workshops Junqing Zhang, Alan Marshall, Roger F. Woods, Trung Quang Duong
2013	Misc	`conf`	Implementation of selective packet destruction on wireless open-access research platform. ACSSC S. Hughes, B. Zhou, Roger F. Woods, Alan Marshall
2013	—	`ch.`	Mapping Decidable Signal Processing Graphs into FPGA Implementations. Handbook of Signal Processing Systems Roger F. Woods
2013	J	`jnl`	Optimization of Weighted Finite State Transducer for Speech Recognition. IEEE Trans. Computers Louis-Marie Aubert, Roger F. Woods, Scott Fischaber, Richard Veitch
2013	J	`jnl`	Power Efficient, FPGA Implementations of Transform Algorithms for Radar-Based Digital Receiver Applications. IEEE Trans. Ind. Informatics Stephen McKeown, Roger F. Woods
2012	J	`jnl`	An On-Demand Queue Management Architecture for a Programmable Traffic Manager. IEEE Trans. Very Large Scale Integr. Syst. Qi Zhang, Roger F. Woods, Alan Marshall
2012	—	`conf`	Novel Application of Genetic Sequencing Algorithms to Optimization of Hardware Resource Sharing for DSP. ASAP Stephen McKeown, Roger F. Woods
2012	J	`jnl`	Preface - ARC. Microprocess. Microsystems Andreas Koch, Roger F. Woods
2012	—	`conf`	Session TA5b: Computer arithmetic accelerators for signal processing. ACSCC Roger F. Woods
2011	—	`conf`	A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection. ARC Xuezheng Chu, John McAllister, Roger F. Woods
2011	J	`jnl`	A Scalable and Programmable Modular Traffic Manager Architecture. ACM Trans. Reconfigurable Technol. Syst. Shane O'Neill, Roger F. Woods, Alan Marshall, Qi Zhang
2011	—	`conf`	Design and implementation of a flexible Queue Manager for Next Generation Networks. ACSCC Qi Zhang, Roger F. Woods, Alan Marshall
2011	J	`jnl`	FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition. Int. J. Reconfigurable Comput. Richard Veitch, Louis-Marie Aubert, Roger F. Woods, Scott Fischaber
2011	—	`conf`	How Resistant are Sboxes to Power Analysis Attacks? NTMS Keanhong Boey, Máire O'Neill, Roger F. Woods
2011	J	`jnl`	Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality. IET Comput. Digit. Tech. Stephen McKeown, Roger F. Woods
2011	J	`jnl`	Real-Valued Fixed-Complexity Sphere Decoder for High Dimensional QAM-MIMO Systems. IEEE Trans. Signal Process. C. Zheng, Xuezheng Chu, John McAllister, Roger F. Woods
2011	—	`ed.`	Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings ARC Andreas Koch, Ram Krishnamurthy, John McAllister, Roger F. Woods, Tarek A. El-Ghazawi
2011	—	`conf`	Session MA8b1: Computer arithmetic I. ACSCC Roger F. Woods
2010	J	`jnl`	A Programmable Architecture for Layered Multimedia Streams in IPv6 Networks. J. Networks Brendan McAllister, Alan Marshall, Roger F. Woods
2010	Misc	`conf`	Adapting noisy speech models - Extended uncertainty decoding. ICASSP Jianhua Lu, Ji Ming, Roger F. Woods
2010	—	`conf`	Design of a flexible high-speed FPGA-based flow monitor for next generation networks. ICSAMOS John McGlone, Roger F. Woods, Alan Marshall, Michaela Blott
2010	—	`conf`	Differential Power Analysis of CAST-128. ISVLSI Keanhong Boey, Yingxi Lu, Máire O'Neill, Roger F. Woods
2010	J	`jnl`	Guest Editorial ARC 2009. ACM Trans. Reconfigurable Technol. Syst. Roger F. Woods, Jürgen Becker, Peter Athanas, Fearghal Morgan
2010	—	`ch.`	Mapping Decidable Signal Processing Graphs into FPGA Implementations. Handbook of Signal Processing Systems Roger F. Woods
2010	—	`conf`	Random clock against differential power analysis. APCCAS Keanhong Boey, Yingxi Lu, Máire O'Neill, Roger F. Woods
2010	—	`conf`	Security of AES Sbox designs to power analysis. ICECS Keanhong Boey, Philip Hodgers, Yingxi Lu, Máire O'Neill, Roger F. Woods
2010	J	`jnl`	SoC Memory Hierarchy Derivation from Dataflow Graphs. J. Signal Process. Syst. Scott Fischaber, Roger F. Woods, John McAllister
2009	—	`conf`	A traffic manager for integrated queuing and scheduling of unicast and multicast IP traffic. ICT Qi Zhang, Alan Marshall, Roger F. Woods
2009	—	`conf`	An Attack-Resilent Sampling Mechanism for Integrated IP Flow Monitors. ICDCS Workshops John McGlone, Alan Marshall, Roger F. Woods
2009	J	`jnl`	Introduction to the Special Issue ARC'08. ACM Trans. Reconfigurable Technol. Syst. Katherine Compton, Roger F. Woods, Christos-Savvas Bouganis, Pedro C. Diniz
2009	—	`ed.`	Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings ARC Jürgen Becker, Roger F. Woods, Peter M. Athanas, Fearghal Morgan
2009	A	`conf`	Replacing uncertainty decoding with subband re-estimation for large vocabulary speech recognition in noise. INTERSPEECH Jianhua Lu, Ji Ming, Roger F. Woods
2008	B	`conf`	A real-time flow monitor architecture encompassing on-demand monitoring functions. NOMS John McGlone, Alan Marshall, Roger F. Woods
2008	A	`conf`	Combining noise compensation and missing-feature decoding for large vocabulary speech recognition in noise. INTERSPEECH Jianhua Lu, Ji Ming, Roger F. Woods
2008	J	`jnl`	Current Trends on Reconfigurable Computing. Int. J. Reconfigurable Comput. Jürgen Becker, Michael Hübner, Roger F. Woods, Philip Heng Wai Leong, Robert Esser, Lionel Torres
2008	J	`jnl`	From Bit Level Systolic Arrays to HDTV Processor Chips. J. Signal Process. Syst. Roger F. Woods, John V. McCanny, John G. McWhirter
2008	—	`conf`	Memory-Centric Hardware Synthesis from Dataflow Models. SAMOS Scott Fischaber, John McAllister, Roger F. Woods
2008	—	`conf`	Novel percussive Instrument Design - Converting Mathematical Formulae into engaging Musical Instruments. ICMC Katarzyna Chuchacz, Roger F. Woods, Sile O'Modhrain
2008	B	`conf`	Power efficient DSP datapath configuration methodology for FPGA. FPL Stephen McKeown, Roger F. Woods, John McAllister
2008	—	`conf`	Power efficient dynamic-range utilisation for DSP on FPGA. SiPS Stephen McKeown, Roger F. Woods, John McAllister
2008	—	`conf`	QR Recursive Least Squares IP Core Example. ECBS Gaye Lightbody, Roger F. Woods
2008	—	`ed.`	Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings ARC Roger F. Woods, Katherine Compton, Christos-Savvas Bouganis, Pedro C. Diniz
2007	J	`jnl`	Design Methodology for Real-Time FPGA-Based Sound Synthesis. IEEE Trans. Signal Process. Erdem Motuk, Roger F. Woods, Stefan Bilbao, John McAllister
2007	—	`conf`	Physical Models and Musical Controllers - Designing a Novel Electronic Percussion Instrument. NIME Katarzyna Chuchacz, Sile O'Modhrain, Roger F. Woods
2007	J	`jnl`	Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms. J. Syst. Archit. John McAllister, Roger F. Woods, Scott Fischaber, E. Malins
2007	—	`conf`	SOC Memory Hierarchy Derivation from Dataflow Graphs. SiPS Scott Fischaber, Roger F. Woods, John McAllister
2007	B	`conf`	Soft IP core implementation of recursive least squares filter using only multplicative and additive operators. FPL Gaye Lightbody, Roger F. Woods, Jonathan Francey
2007	J	`jnl`	Transforming Signal Processing Applications into Parallel Implementations. EURASIP J. Adv. Signal Process. Ed F. Deprettere, Roger F. Woods, Ingrid Verbauwhede, Erwin A. de Kock
2006	—	`conf`	From Bit Level Systolic Arrays to HDTV Processor Chips. ASAP John V. McCanny, Roger F. Woods, John G. McWhirter
2006	J	`jnl`	Hierarchical synthesis of complex DSP functions using IRIS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Yi, Roger F. Woods
2006	—	`conf`	Muir Hardware Synthesis for Multimedia Applications. ESTIMedia Scott Fischaber, John McAllister, Roger F. Woods, E. Malins
2006	J	`jnl`	Multidimensional DSP Core Synthesis for FPGA. J. VLSI Signal Process. John McAllister, Roger F. Woods, Richard L. Walke, Darren Gerard Reilly
2006	C	`conf`	Providing Input-Output Throughput Guarantees in a Buffered Crossbar Switch. ISCC Shane O'Neill, Alan Marshall, Roger F. Woods
2005	B	`conf`	A Novel Packet Marking Function for Real-Time Interactive MPEG-4 Video Applications in a Differentiated Services Network. NETWORKING Shane O'Neill, Alan Marshall, Roger F. Woods
2005	—	`conf`	FPGA Core Network Implementation and Optimization: A Case Study. FPT Scott Fischaber, R. Hasson, John McAllister, Roger F. Woods
2005	—	`conf`	FPGA-Based Hardware for Physical Modelling Sound Synthesis by Finite Difference Schemes. FPT Erdem Motuk, Roger F. Woods, Stefan Bilbao
2005	J	`jnl`	High Speed FPGA-Based Implementations of Delayed-LMS Filters. J. VLSI Signal Process. Ying Yi, Roger F. Woods, Lok-Kee Ting, C. F. N. Cowan
2005	—	`conf`	Implementation of finite difference schemes for the wave equation on FPGA. ICASSP (3) Erdem Motuk, Roger F. Woods, Stefan Bilbao
2005	—	`conf`	Parallel implementation of finite difference schemes for the plate equation on a FPGA-based multi-processor array. EUSIPCO Erdem Motuk, Roger F. Woods, Stefan Bilbao
2005	—	`conf`	Programmable Network Functionality for Improved QoS of Interactive Video Traffic. Net-Con Brendan McAllister, Alan Marshall, Roger F. Woods
2005	—	`conf`	Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms. SAMOS John McAllister, Roger F. Woods, Darren Gerard Reilly, Scott Fischaber, R. Hasson
2005	—	`conf`	Rapid generation of hardware functionality in heterogeneous platforms [FPGA implementation applications]. ICASSP (5) Darren Gerard Reilly, Roger F. Woods, John McAllister, Richard L. Walke
2005	J	`jnl`	Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers. IEEE Trans. Very Large Scale Integr. Syst. Lok-Kee Ting, Roger F. Woods, C. F. N. Cowan
2004	—	`conf`	Embedded Context Aware Hardware Component Generation for Dataflow System Exploration. SAMOS John McAllister, Roger F. Woods, Richard L. Walke
2004	J	`jnl`	Guest Editorial: Field Programmable Logic. J. VLSI Signal Process. Roger F. Woods, Russell Tessier
2004	J	`jnl`	Highly efficient, limited range multipliers for LUT-based FPGA architectures. IEEE Trans. Very Large Scale Integr. Syst. Richard H. Turner, Roger F. Woods
2004	J	`jnl`	LMS coefficient filtering for Time-varying chirped signals. IEEE Trans. Signal Process. Lok-Kee Ting, Colin F. N. Cowan, Roger F. Woods
2003	B	`conf`	Design Flow for Efficient FPGA Reconfiguration. FPL Richard H. Turner, Roger F. Woods
2003	J	`jnl`	Design of a parameterizable silicon intellectual property core for QR-based RLS filtering. IEEE Trans. Very Large Scale Integr. Syst. Gaye Lightbody, Roger F. Woods, Richard L. Walke
2002	—	`conf`	FPGA-based system-level design framework based on the IRIS synthesis tool and System Generator. FPT Ying Yi, Roger F. Woods
2002	Misc	`conf`	Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXes. FCCM Tim Courtney, Richard H. Turner, Roger F. Woods
2002	B	`conf`	Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs. FPL Richard H. Turner, Roger F. Woods, Tim Courtney
2001	J	`jnl`	Advances in adaptive signal processing: totally adaptive systems. Annu. Rev. Control. Colin Cowan, Roger F. Woods, Jean-Paul Heron, P. Power, F. J. Sweeney
2001	J	`jnl`	Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead. J. VLSI Signal Process. Jean-Paul Heron, Roger F. Woods, Sakir Sezer, Richard H. Turner
2001	B	`ed.`	Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings FPL Gordon J. Brebner, Roger F. Woods
2001	Misc	`conf`	Implementation of fixed DSP functions using the reduced coefficient multiplier. ICASSP Richard H. Turner, Tim Courtney, Roger F. Woods
2001	B	`conf`	Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver. FPL Lok-Kee Ting, Roger F. Woods, Colin Cowan
2000	Misc	`conf`	An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing. FCCM Tim Courtney, Richard H. Turner, Roger F. Woods
2000	J	`jnl`	Linear QR Architecture for a Single Chip Adaptive Beamformer. J. VLSI Signal Process. Gaye Lightbody, Richard L. Walke, Roger F. Woods, John V. McCanny
2000	B	`conf`	Multiplexer Based Reconfiguration for Virtex Multipliers. FPL Tim Courtney, Richard H. Turner, Roger F. Woods
2000	—	`conf`	Tracking performance of momentum LMS algorithm for a chirped sinusoidal signal. EUSIPCO Lok-Kee Ting, C. F. N. Cowan, Roger F. Woods
1999	Misc	`conf`	A Virtual Hardware Handler for RTR Systems. FCCM Richard H. Turner, Roger F. Woods, Sakir Sezer, Jean-Paul Heron
1999	Misc	`conf`	Accelerating Run-Time Reconfiguration on FCCMs. FCCM Jean-Paul Heron, Roger F. Woods
1999	Misc	`conf`	Novel mapping of a linear QR architecture. ICASSP Gaye Lightbody, Richard L. Walke, Roger F. Woods, John V. McCanny
1998	J	`jnl`	Applying an XC6200 to Real-Time Image Processing. IEEE Des. Test Comput. Roger F. Woods, David W. Trainor, Jean-Paul Heron
1998	Misc	`conf`	Fast Partial Reconfiguration for FCCMs. FCCM Sakir Sezer, Roger F. Woods, Jean-Paul Heron, Alan Marshall
1998	A	`conf`	The impact of data characteristics and hardware topology on hardware selection for low power DSP. ISLPED Gareth Keane, Jonathan R. Spanier, Roger F. Woods
1998	—	`conf`	The impact of data characteristics on hardware selection for low-power DSP. EUSIPCO Gareth Keane, Jonathan R. Spanier, Roger F. Woods
1997	J	`jnl`	Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS". J. VLSI Signal Process. David W. Trainor, Roger F. Woods, John V. McCanny
1997	Misc	`conf`	FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again). FCCM Roger F. Woods, Stefan H.-M. Ludwig, Jean-Paul Heron, David W. Trainor, Stephan W. Gehring
1996	J	`jnl`	A 64-point Fourier transform chip for video motion compensation using phase correlation. IEEE J. Solid State Circuits Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods
1996	—	`conf`	A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation. ASAP Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods
1996	B	`conf`	Architectural Strategies for Implementing an Image Processing Algorithm on XC6000 FPGA. FPL Jean-Paul Heron, Roger F. Woods
1996	B	`conf`	Architectural Synthesis and Efficient Circuit Implementation for Field Programmable Gate Arrays. FPL David W. Trainor, Roger F. Woods
1996	—	`conf`	Error analysis of FFT architectures for digital video applications. ICECS Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods
1996	Misc	`conf`	VLSI architectures for field programmable gate arrays: a case study. FCCM Roger F. Woods, A. Cassidy, J. Gray
1994	—	`conf`	A high performance IIR filter chip and its evaluation system. ASAP Richard L. Walke, Roger Evans, Roger F. Woods, G. Floyd, K. W. Wood
1992	Misc	`conf`	The systematic design of high performance digital filters. ICASSP B. P. McGovern, Roger F. Woods, John V. McCanny
1991	—	`conf`	A 40 megasample IIR filter chip. ASAP O. C. McNally, John V. McCanny, Roger F. Woods
1991	—	`conf`	Design of a Highly Pipelined 2nd Order IIR Filter Chip. VLSI O. C. McNally, John V. McCanny, Roger F. Woods
1990	C	`conf`	Optimized bit level architectures for IIR filtering. ICCD O. C. McNally, John V. McCanny, Roger F. Woods
1990	Misc	`conf`	Pipelined two-port adaptor for wave digital filtering. ICASSP Rajinder Jit Singh, John V. McCanny, Roger F. Woods
1989	Misc	`conf`	A bit-level systolic architecture for very high performance IIR filters. ICASSP Simon C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny
1989	J	`jnl`	Bit-Level systolic architectures for high performance IIR filtering. J. VLSI Signal Process. Simon C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny
1988	Misc	`conf`	Systolic IIR filters with bit level pipelining. ICASSP Roger F. Woods, Simon C. Knowles, John V. McCanny, John G. McWhirter