Roger Espasa - RankMe

43 papers A* 10A 5B 2C 3Misc 1Journal 9Unranked 13

Year	Rank	Type	Title / Venue / Authors
2021	—	`conf`	Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip. HCS David R. Ditzel, Roger Espasa, Nivard Aymerich, Allen Baum, Tom Berg, Jim Burr, Eric Hao, Jayesh Iyer, Miquel Izquierdo, Shankar Jayaratnam, Darren Jones, Chris Klingner, Jin Kim, Stephen Lee, Marc Lupon, Grigorios Magklis, Bojan Maric, Rajib Nath, Mike Neilly, J. Duane Northcutt, Bill Orner, Jose Renau, Gerard Reves, Xavier Reves, Tom Riordan, Pedro Sanchez, Sridhar Samudrala, Guillem Sole, Raymond Tang, Tommy Thorn, Francisco Torres, Sebastia Tortella, Daniel Yau
2010	J	`jnl`	A SIMD-efficient 14 instruction shader program for high-throughput microtriangle rasterization. Vis. Comput. Jordi Roca, Victor Moya Del Barrio, Carlos González, Vicente Escandell, Albert Murciego, Agustín Fernández, Roger Espasa
2010	—	`conf`	Larrabee: A Many-Core Intel Architecture for Visual Computing. HiPEAC Roger Espasa
2009	J	`jnl`	Larrabee: A Many-Core x86 Architecture for Visual Computing. IEEE Micro Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Pradeep Dubey, Stephen Junkins, Adam T. Lake, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Michael Abrash, Jeremy Sugerman, Pat Hanrahan
2008	J	`jnl`	Larrabee: a many-core x86 architecture for visual computing. ACM Trans. Graph. Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam T. Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan
2006	B	`conf`	ATTILA: a cycle-level execution-driven simulator for modern GPU architectures. ISPASS Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa
2006	—	`conf`	Workload Characterization of 3D Games. IISWC Jordi Roca, Victor Moya Del Barrio, Carlos González, Chema Solis, Agustín Fernández, Roger Espasa
2005	—	`conf`	A Single (Unified) Shader GPU Microarchitecture for Embedded Systems. HiPEAC Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa
2005	J	`jnl`	Conflict-Free Accesses to Strided Vectors on a Banked Cache. IEEE Trans. Computers André Seznec, Roger Espasa
2005	A*	`conf`	Shader Performance Analysis on a Modern GPU Architecture. MICRO Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustín Fernández, Roger Espasa
2004	—	`conf`	Link-Time Optimization Techniques for Eliminating Conditional Branch Redundancies. Interaction between Compilers and Computer Architectures Manel Fernández, Roger Espasa
2004	A*	`conf`	Link-Time Path-Sensitive Memory Redundancy Elimination. HPCA Manel Fernández, Roger Espasa
2003	J	`jnl`	A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications. Theory Comput. Syst. Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
2003	J	`jnl`	Load redundancy elimination on executable code. Concurr. Comput. Pract. Exp. Manel Fernández, Roger Espasa, Saumya K. Debray
2002	J	`jnl`	Asim: A Performance Model Framework. Computer Joel S. Emer, Pritpal S. Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan
2002	—	`conf`	Speculative Alias Analysis for Executable Code. IEEE PACT Manel Fernández, Roger Espasa
2002	A*	`conf`	Tarantula: A Vector Extension to the Alpha Architecture. ISCA Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec
2002	A*	`conf`	Three-dimensional memory vectorization for high bandwidth media memory systems. MICRO Jesús Corbal, Roger Espasa, Mateo Valero
2001	B	`conf`	A cost effective architecture for vectorizable numerical and multimedia applications. SPAA Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
2001	A*	`conf`	DLP + TLP Processors for the Next Generation of Media Workloads. HPCA Jesús Corbal, Roger Espasa, Mateo Valero
2001	—	`conf`	Load Redundancy Elimination on Executable Code. Euro-Par Manel Fernández, Roger Espasa, Saumya K. Debray
2001	—	`conf`	On the Efficiency of Reductions in µ-SIMD Media Extensions. IEEE PACT Jesús Corbal, Roger Espasa, Mateo Valero
2001	—	`conf`	Topic 08+13: Instruction-Level Parallelism and Computer Architecture. Euro-Par Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec
1999	J	`jnl`	A Simulation Study of Decoupled Vector Architectures. J. Supercomput. Roger Espasa, Mateo Valero
1999	A	`conf`	Adding a vector unit to a superscalar processor. International Conference on Supercomputing Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
1999	A*	`conf`	Exploiting a New Level of DLP in Multimedia Applications. MICRO Jesús Corbal, Roger Espasa, Mateo Valero
1999	A	`conf`	MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications. SC Jesús Corbal, Roger Espasa, Mateo Valero
1998	A	`conf`	A Performance Study of Out-of-order Vector Architectures and Short Registers. International Conference on Supercomputing Luis Villa, Roger Espasa, Mateo Valero
1998	C	`conf`	A case for merging the ILP and DLP paradigms. PDP Francisca Quintana, Roger Espasa, Mateo Valero
1998	—	`conf`	An ISA Comparison Between Superscalar and Vector Processors. VECPAR Francisca Quintana, Roger Espasa, Mateo Valero
1998	—	`conf`	Command Vector Memory Systems: High Performance at Low Cost. IEEE PACT Jesús Corbal, Roger Espasa, Mateo Valero
1998	A*	`conf`	Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes. MICRO Alexandre Farcy, Olivier Temam, Roger Espasa, Toni Juan
1998	C	`conf`	Effective usage of vector registers in decoupled vector architectures. PDP Luis Villa, Roger Espasa, Mateo Valero
1998	—	`conf`	Registers Size Influence on Vector Architectures. VECPAR Luis Villa, Roger Espasa, Mateo Valero
1998	A	`conf`	Vector Architectures: Past, Present and Future. International Conference on Supercomputing Roger Espasa, Mateo Valero, James E. Smith
1997	A	`conf`	A Victim Cache for Vector Registers. International Conference on Supercomputing Roger Espasa, Mateo Valero
1997	—	`conf`	Effective Usage of Vector Registers in Advanced Vector Architectures. IEEE PACT Luis Villa, Roger Espasa, Mateo Valero
1997	J	`jnl`	Exploiting instruction- and data-level parallelism. IEEE Micro Roger Espasa, Mateo Valero
1997	A*	`conf`	Multithreaded Vector Architectures. HPCA Roger Espasa, Mateo Valero
1997	A*	`conf`	Out-of-Order Vector Architectures. MICRO Roger Espasa, Mateo Valero, James E. Smith
1997	Misc	`conf`	Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance. HiPC Roger Espasa, Mateo Valero
1996	A*	`conf`	Decoupled Vector Architectures. HPCA Roger Espasa, Mateo Valero
1995	C	`conf`	Quantitative analysis of vector code. PDP Roger Espasa, Mateo Valero, David A. Padua, Marta Jiménez, Eduard Ayguadé