Roberto Suaya

19 papers A* 1A 5C 1Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2019 — conf
Low Power SPI Design Based on Relative Timing Techniques.
ICECS
Guillermo H. Makar, Francisco J. Badenas, Roberto G. Simone, Alejandro Furfaro, Kenneth S. Stevens, Roberto Suaya
2013 — conf
Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nm.
NOCS
Shomit Das, Georgios Manetas, Kenneth S. Stevens, Roberto Suaya
2012 A conf
An efficient framework for passive compact dynamical modeling of multiport linear systems.
DATE
Zohaib Mahmood, Roberto Suaya, Luca Daniel
2012 J jnl
Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee
2010 J jnl
Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee
2010 A conf
Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate.
DATE
Navin Srivastava, Roberto Suaya, Kaustav Banerjee
2009 J jnl
Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Navin Srivastava, Roberto Suaya, Kaustav Banerjee
2008 A conf
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate.
DATE
Navin Srivastava, Roberto Suaya, Kaustav Banerjee
2007 — conf
Efficient implementation of conduction modes for modelling skin effect.
ISVLSI
Salvador Ortiz, Roberto Suaya
2006 A conf
Fullwave volumetric Maxwell solver using conduction modes.
ICCAD
Salvador Ortiz, Roberto Suaya
2006 C conf
Mutual inductance between intentional inductors: closed form expressions.
ISCAS
Rafael Escovar, Salvador Ortiz, Roberto Suaya
2005 J jnl
An improved long distance treatment for mutual inductance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rafael Escovar, Salvador Ortiz, Roberto Suaya
2005 — conf
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?
ASP-DAC
Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen
2004 — conf
Mutual inductance extraction and the dipole approximation.
ISPD
Rafael Escovar, Salvador Ortiz, Roberto Suaya
2004 J jnl
Optimal design of clock trees for multigigahertz applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rafael Escovar, Roberto Suaya
2002 A conf
Transmission line design of clock trees.
ICCAD
Rafael Escovar, Roberto Suaya
1991 A* conf
A Two-Dimensional Topological Compactor With Octagonal Geometry.
DAC
Paul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya
1991 — conf
From formal verification to silicon compilation.
Compcon
Jeffrey Joyce, Erwin Liu, John M. Rushby, Natarajan Shankar, Roberto Suaya, Friedrich W. von Henke
1990 J jnl
Two-dimensional IC layout compaction based on topological design rule checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
John Valainis, Sinan Kaptanoglu, Erwin Liu, Roberto Suaya