Roberto R. Osorio

36 papers B 1C 7Misc 1Journal 14Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	Misc	`conf`	Accelerating Scientific Model Optimization with a Pipelined FPGA-Based Differential Evolution Engine. FCCM Manuel de Castro, Roberto R. Osorio, Yuri Torres, Diego R. Llanos
2025	J	`jnl`	Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application. IEEE Access Manuel de Castro, Roberto R. Osorio, Francisco J. Andújar, Rocío Carratalá-Sáez, Yuri Torres, Diego R. Llanos
2024	—	`conf`	Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL. Euro-Par Workshops (1) Manuel de Castro, Roberto R. Osorio, Francisco J. Andújar, Rocío Carratalá-Sáez, Yuri Torres, Diego R. Llanos
2024	J	`jnl`	Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL. CoRR Manuel de Castro, Francisco J. Andújar, Roberto R. Osorio, Rocío Carratalá-Sáez, Diego R. Llanos
2024	J	`jnl`	Finite-Time Lyapunov Exponent Calculation on FPGA using High-Level Synthesis Tools. CoRR Manuel de Castro, Roberto R. Osorio, Francisco J. Andujar, Rocío Carratalá-Sáez, Yuri Torres, Diego R. Llanos
2023	J	`jnl`	Floating Point Calculation of the Cube Function on FPGAs. IEEE Trans. Parallel Distributed Syst. Roberto R. Osorio
2023	J	`jnl`	Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL. J. Supercomput. Manuel de Castro, Roberto R. Osorio, David López Vilariño, Arturo González-Escribano, Diego R. Llanos
2022	J	`jnl`	An efficient ant colony optimization framework for HPC environments. Appl. Soft Comput. Patricia González, Roberto R. Osorio, Xoán C. Pardo, Julio R. Banga, Ramón Doallo
2019	C	`conf`	A Microprogrammed Approach for Implementing Statecharts. DSD Javier Cereijo García, Roberto R. Osorio
2019	—	`conf`	Hardware Implementation of Statecharts for FPGA-based Control in Scientific Facilities. DCIS Javier Cereijo García, Roberto R. Osorio
2019	J	`jnl`	Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors. IEEE Access Roberto R. Osorio, Gabriel Rodríguez
2016	J	`jnl`	A fast algorithm for constructing nearly optimal prefix codes. Softw. Pract. Exp. Roberto R. Osorio, Patricia González
2016	—	`conf`	Pipelined FPGA implementation of numerical integration of the Hodgkin-Huxley model. ASAP Roberto R. Osorio
2013	C	`conf`	Architecture and Implementation of a Data Compression System at Switch-Level in ATA-over-Ethernet Storage Networks. DSD Angela Souto Vieites, Roberto R. Osorio
2013	J	`jnl`	High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard. J. Signal Process. Syst. Roberto R. Osorio, Javier D. Bruguera
2013	J	`jnl`	Improving Scalability of Application-Level Checkpoint-Recovery by Reducing Checkpoint Sizes. New Gener. Comput. Iván Cores, Gabriel Rodríguez, María J. Martín, Patricia González, Roberto R. Osorio
2012	B	`conf`	Fast Construction of Nearly-Optimal Prefix Codes without Probability Sorting. DCC Roberto R. Osorio, Patricia González
2011	J	`jnl`	Performance analysis of massively parallel embedded hardware architectures for retinal image processing. EURASIP J. Image Video Process. Alejandro Nieto, Víctor M. Brea, David López Vilariño, Roberto R. Osorio
2009	—	`conf`	A digital cellular-based system for retinal vessel-tree extraction. ECCTD Cesar Diaz-Resco, Alejandro Nieto, Roberto R. Osorio, Víctor M. Brea, David López Vilariño
2009	C	`conf`	High Performance Image Processing on a Massively Parallel Processor Array. DSD Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bruguera
2008	—	`conf`	An FPGA architecture for CABAC decoding in manycore systems. ASAP Roberto R. Osorio, Javier D. Bruguera
2007	—	`conf`	Entropy Coding on a Programmable Processor Array for Multimedia SoC. ASAP Roberto R. Osorio, Javier D. Bruguera
2006	C	`conf`	A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems. DSD Roberto R. Osorio, Javier D. Bruguera
2006	C	`conf`	A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. DSD Javier D. Bruguera, Roberto R. Osorio
2006	J	`jnl`	High-Throughput Architecture for H.264/AVC CABAC Compression System. IEEE Trans. Circuits Syst. Video Technol. Roberto R. Osorio, Javier D. Bruguera
2005	C	`conf`	A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. DSD Roberto R. Osorio, Javier D. Bruguera
2004	C	`conf`	Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. DSD Roberto R. Osorio, Javier D. Bruguera
2004	J	`jnl`	View-dependent, scalable texture streaming in 3-D QoS with MPEG-4 visual texture coding. IEEE Trans. Circuits Syst. Video Technol. Gauthier Lafruit, Eric Delfosse, Roberto R. Osorio, Wolfgang van Raemdonck, Vissarion Ferentinos
2003	J	`jnl`	High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based Compression. J. VLSI Signal Process. Roberto R. Osorio, Bart Vanhoof
2002	—	`conf`	Bitstream Syntax Description Language for 3D MPEG-4 view-dependent texture streaming. ICIP (3) Roberto R. Osorio, Sylvain Devillers, Eric Delfosse, Myriam Amielh, Gauthier Lafruit
2000	—	`conf`	Architectures for arithmetic coding in image compression. EUSIPCO Roberto R. Osorio, Javier D. Bruguera
1999	—	`conf`	New model for arithmetic coding/decoding of multilevel images based on a cache memory. ICECS Roberto R. Osorio, Javier D. Bruguera
1998	—	`conf`	Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory. EUROMICRO Roberto R. Osorio, Montserrat Bóo, Javier D. Bruguera
1997	—	`conf`	A VLSI implementation of an arithmetic coder for image compression. EUROMICRO Mercedes Peón, Roberto R. Osorio, Javier D. Bruguera
1997	—	`conf`	New arithmetic coder/decoder architectures based on pipelining. ASAP Roberto R. Osorio, Javier D. Bruguera
1995	—	`conf`	Digit On-line Large Radix CORDIC Rotator. ASAP Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata