Roberto Nonis

35 papers C 4Journal 14Unranked 16
YearRankTypeTitle / Venue / Authors
2025 C conf
A -44dB PSRR Analog Nested Digital Low Dropout Regulator for SoC applications in CMOS 28nm.
ISCAS
Stefano Bonomi, Werner Grollitsch, Sie Boo Chiang, Roberto Nonis
2023 J jnl
A 5-V Switch for Analog Multiplexers With 2.5-V Transistors in 28-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Giuseppe E. Biccario, Oleg Vitrenko, Roberto Nonis, Stefano D'Amico
2023 J jnl
A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap.
Alessio Cortiula, Davide Menin, Andrea Bandiziol, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
2021 J jnl
A 1.6-V Tolerant Multiplexer Switch With 0.96-V Core Devices in 28-nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Giuseppe E. Biccario, Oleg Vitrenko, Roberto Nonis, Stefano D'Amico
2021 J jnl
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation.
IEEE Trans. Very Large Scale Integr. Syst.
Pierpaolo Palestri, Ahmed Elnaqib, Davide Menin, Klaid Shyti, Francesco Brandonisio, Andrea Bandiziol, Davide Rossi, Roberto Nonis
2020 C conf
Analysis of Spurs Impact in PLL-Based FMCW Radar Systems.
ISCAS
Luigi Grimaldi, Dmytro Cherniak, Werner Grollitsch, Roberto Nonis
2020 J jnl
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Davide Menin, Andrea Bandiziol, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
2019 — conf
A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion.
ESSCIRC
Alessandro Franceschin, Pietro Andreani, Fabio Padovan, Matteo Bassi, Roberto Nonis, Andrea Bevilacqua
2019 — conf
A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces.
MIPRO
Alessio Cortiula, Martino Dazzi, Mattia Marcon, Davide Menin, Marco Scapol, Andrea Bandiziol, Andrea Cristofoli, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
2019 — conf
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers.
APCCAS
Dylan D'Ampolo, Andrea Bandiziol, Davide Menin, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
2018 J jnl
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation.
IEEE J. Solid State Circuits
Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi, Roberto Nonis, Carlo Samori, Salvatore Levantino
2018 — conf
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation.
ISSCC
Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi, Carlo Samori, Roberto Nonis, Salvatore Levantino
2018 J jnl
Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Bandiziol, Werner Grollitsch, Giovanni Steffan, Roberto Nonis, Pierpaolo Palestri
2018 C conf
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm.
ISCAS
Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Matteo Bassi, Roberto Nonis, Pierpaolo Palestri
2018 — conf
Low noise active loop filter for radar PLL applications.
ICICDT
Andrea Donno, Stefano D'Amico, Roberto Nonis, Peter Thurner
2018 J jnl
On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs
Alessandro Franceschin, Fabio Padovan, Roberto Nonis, Andrea Bevilacqua
2018 J jnl
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dmytro Cherniak, Carlo Samori, Roberto Nonis, Salvatore Levantino
2018 — conf
Session 25 overview: Clock generation for high-speed links: Wireline subcommittee.
ISSCC
Roberto Nonis, Pavan Kumar Hanumolu, Frank O'Mahony
2017 C conf
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars.
ISCAS
Dmytro Chemiak, Salvatore Levantino, Carlo Samori, Roberto Nonis
2017 — conf
F2: High-performance frequency generation for wireless and wireline systems.
ISSCC
Jiayoon Ru, Kohei Onizuka, Pavan Kumar Hanumolu, Roberto Nonis, Howard C. Luong, Jan Craninckx
2016 — conf
A fractional-N, all-digital injection-locked PLL with wide tuning range digitally controlled ring oscillator and Bang-Bang phase detection for temperature tracking in 40nm CMOS.
ESSCIRC
Werner Grollitsch, Roberto Nonis
2016 — conf
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers.
APCCAS
Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri
2016 — conf
Design of a transmitter for high-speed serial interfaces in automotive micro-controller.
MIPRO
Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri
2016 — conf
Session 10 overview: Advanced wireline transceivers and PLLs.
ISSCC
Jaeha Kim, Roberto Nonis
2015 — conf
Design, characterization and signal integrity analysis of a 2.5 Gb/s High-Speed Serial Interface for automotive applications overarching the chip/PCB wall.
RTSI
Andrea Cossettini, Andrea Cristofoli, Werner Grollitsch, Lino Alves, Roberto Nonis, Luca Della Ricca, Pierpaolo Palestri, Luca Selmi
2015 — conf
Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters.
ESSCIRC
Dmytro Cherniak, Michael Aichner, Roberto Nonis, Nicola Da Dalt
2013 — conf
A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider.
ISSCC
Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt
2013 J jnl
digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture.
IEEE J. Solid State Circuits
Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt
2010 — conf
A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS.
ISSCC
Werner Grollitsch, Roberto Nonis, Nicola Da Dalt
2010 J jnl
A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators.
Int. J. Circuit Theory Appl.
Michele Nocente, Donald Fontanelli, Pierpaolo Palestri, Roberto Nonis, David Esseni, Luca Selmi
2008 J jnl
Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Luca Bizjak, Nicola Da Dalt, Peter Thurner, Roberto Nonis, Pierpaolo Palestri, Luca Selmi
2007 J jnl
A Design Methodology for MOS Current-Mode Logic Frequency Dividers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Roberto Nonis, Enzo Palumbo, Pierpaolo Palestri, Luca Selmi
2007 — —
Modeling and design of low power integrated circuits for frequency synthesis in CMOS technology.
Roberto Nonis
2005 J jnl
Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture.
IEEE J. Solid State Circuits
Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi
2004 — conf
Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture.
ISCAS (4)
Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, Luca Selmi