Roberto Gutiérrez

12 papers B 2C 2Journal 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
Performance, Limitations, and Design Issues of the Integration of a Hardware-Based IME Module With HEVC Video Encoder Software.
IEEE Access
Otoniel López Granado, Héctor Migallón, Estefanía Alcocer, Roberto Gutiérrez, Glenn Van Wallendael, Manuel P. Malumbres
2019 J jnl
Design and implementation of an efficient hardware integer motion estimator for an HEVC video encoder.
J. Real Time Image Process.
Estefanía Alcocer, Roberto Gutiérrez, Otoniel Mario López Granado, Manuel P. Malumbres
2018 J jnl
System-on-Chip for Real-Time Satellite Photovoltaic Curves Telemetry.
IEEE Trans. Ind. Informatics
Roberto Gutiérrez, José M. Blanes, David Marroqui, Ausiàs Garrigós, F. Javier Toledo-Moreo
2017 C conf
Designing Arduino electronic shields: Experiences from secondary and university courses.
EDUCON
Ausiàs Garrigós, David Marroqui, José M. Blanes, Roberto Gutiérrez, I. Blanquer, M. Canto
2015 C conf
Investigation into the potential use of integrated switching regulators for low-voltage, low-power phovotovoltaic conversion in space applications.
IECON
Ausiàs Garrigós, José M. Blanes, Roberto Gutiérrez, Marcos Compadre, Craig Clark, Malcolm Macdonald
2013 J jnl
MPCM: a hardware coder for super slow motion video sequences.
EURASIP J. Adv. Signal Process.
Estefanía Alcocer, Otoniel Mario López Granado, Roberto Gutiérrez, Manuel P. Malumbres
2012 J jnl
Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method.
IEEE Trans. Circuits Syst. II Express Briefs
Roberto Gutiérrez, Vicente Torres-Carot, Javier Valls
2011 J jnl
Low Cost Hardware Implementation of Logarithm Approximation.
IEEE Trans. Very Large Scale Integr. Syst.
Roberto Gutiérrez, Javier Valls
2010 J jnl
FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques.
J. Syst. Archit.
Roberto Gutiérrez, Vicente Torres-Carot, Javier Valls-Coquillat
2009 B conf
FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic.
FPL
Roberto Gutiérrez, Javier Valls, Asuncion Perez-Pascual
2009 J jnl
Low-Power FPGA-Implementation of
J. Signal Process. Syst.
Roberto Gutiérrez, Javier Valls
2007 B conf
Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms.
FPL
Roberto Gutiérrez, Javier Valls